MAX 10 FPGA Development Kit User Guide

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ID 683460
Date 9/07/2017
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Board Test System 4. Board Components A. Additional Information
1. Overview x
1.1. General Description 1.2. Handling the Board
2. Getting Started x
2.1. Quartus II Web Edition Software 2.2. Installing the Development Kit 2.3. Installing the USB-Blaster Driver 2.4. Board Update Portal
3. Board Test System x
3.1. Using the Configure Menu 3.2. The System Info Tab 3.3. The GPIO Tab 3.4. The Flash Tab 3.5. The HSMC Tab 3.6. The DDR3 Tab 3.7. The ADC Tab 3.8. The HDMI Tab 3.9. The Sleep Mode Tab 3.10. The Power Monitor 3.11. The Clock Control
4. Board Components x
4.1. Board Overview 4.2. Featured Device 4.3. Configuration 4.4. Status Elements 4.5. Setup Elements 4.6. General User Input/Output 4.7. Clock Circuitry 4.8. Components and Interfaces 4.9. Memory 4.10. Power Distribution System
4.3. Configuration x
4.3.1. Using the Quartus II Programmer 4.3.2. Selecting the Internal Configuration Scheme 4.3.3. Switch and Jumper Settings
4.7. Clock Circuitry x
4.7.1. On-Board Oscillators 4.7.2. Off-Board Clock Input/Output
4.8. Components and Interfaces x
4.8.1. 10/100/1000 Ethernet PHY 4.8.2. Digital-to-Analog Converter 4.8.3. HDMI Video Output 4.8.4. HSMC 4.8.5. Pmod Connectors 4.8.6. USB to UART
4.9. Memory x
4.9.1. DDR3 Rev. B Board 4.9.2. DDR3 Rev. C Board 4.9.3. Flash
A. Additional Information x
A.1. User Guide Revision History A.2. Compliance and Conformity Statements
A.2. Compliance and Conformity Statements x
A.2.1. CE EMI Conformity Caution
1. Overview
2. Getting Started
3. Board Test System
4. Board Components
A. Additional Information

3.7. The ADC Tab

The ADC Tab (analog-to-digital) shows the real-time voltage values of all of the ADC input channels.

Figure 12. The ADC Tab

The two tables displayed on this tab, ADC 1 and ADC 2 are not editable. The following table shows where the channels connect to.

Dedicated Channel SMA Connector
ADC 1 ANAIN1_SMA(J18)
Channel0 ADC1_CH0(J20.1)
Channel1 ADC1_CH1(J20.3)
Channel2 ADC1_CH2(J20.5)
Channel3 ADC1_CH2(J20.7)
Channel4 ADC1_CH4(J20.11)
Channel5 ADC1_CH4(J20.13)
Channel6 ADC1_CH6(J20.15 or POT1)
Channel7 ADC1_CH7(J20.17)
Dedicated Channel SMA Connector
ADC 2 ANAIN2_SMA(J19)
Channel0 ADC1_CH0(J20.2)
Channel1 ADC1_CH1(J20.4)
Channel2 ADC1_CH2(J20.6)
Channel3 ADC1_CH2(J20.8)
Channel4 ADC1_CH4(J20.12)
Channel5 ADC1_CH4(J20.14)
Channel6 ADC1_CH6(J20.16)
Channel7 ADC1_CH7(J20.18)
Level Two Title