MAX 10 FPGA Development Kit User Guide

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ID 683460
Date 9/07/2017
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Board Test System 4. Board Components A. Additional Information
1. Overview x
1.1. General Description 1.2. Handling the Board
2. Getting Started x
2.1. Quartus II Web Edition Software 2.2. Installing the Development Kit 2.3. Installing the USB-Blaster Driver 2.4. Board Update Portal
3. Board Test System x
3.1. Using the Configure Menu 3.2. The System Info Tab 3.3. The GPIO Tab 3.4. The Flash Tab 3.5. The HSMC Tab 3.6. The DDR3 Tab 3.7. The ADC Tab 3.8. The HDMI Tab 3.9. The Sleep Mode Tab 3.10. The Power Monitor 3.11. The Clock Control
4. Board Components x
4.1. Board Overview 4.2. Featured Device 4.3. Configuration 4.4. Status Elements 4.5. Setup Elements 4.6. General User Input/Output 4.7. Clock Circuitry 4.8. Components and Interfaces 4.9. Memory 4.10. Power Distribution System
4.3. Configuration x
4.3.1. Using the Quartus II Programmer 4.3.2. Selecting the Internal Configuration Scheme 4.3.3. Switch and Jumper Settings
4.7. Clock Circuitry x
4.7.1. On-Board Oscillators 4.7.2. Off-Board Clock Input/Output
4.8. Components and Interfaces x
4.8.1. 10/100/1000 Ethernet PHY 4.8.2. Digital-to-Analog Converter 4.8.3. HDMI Video Output 4.8.4. HSMC 4.8.5. Pmod Connectors 4.8.6. USB to UART
4.9. Memory x
4.9.1. DDR3 Rev. B Board 4.9.2. DDR3 Rev. C Board 4.9.3. Flash
A. Additional Information x
A.1. User Guide Revision History A.2. Compliance and Conformity Statements
A.2. Compliance and Conformity Statements x
A.2.1. CE EMI Conformity Caution
1. Overview
2. Getting Started
3. Board Test System
4. Board Components
A. Additional Information

4.9.3. Flash

The MAX 10 FPGA development kit provides a 512-Mb (megabit) quad SPI flash memory. Altera Generic QUAD SPI controller core is used by default to erase, read, and write quad SPI flash in reference designs of the Board Test System (BTS) installer.

If you use the parallel flash loader (PFL) IP to program the quad SPI flash, you need to generate a .pof (Programmer Object file) to configure the device.

Perform the following steps to generate a .pof file:

  1. Create a byte-order Quartus.ini file with the setting:

    PGMIO_SWAP_HEX_BYTE_DATA=ON

  2. Copy the .ini file to the project root directory and open the project with Quartus
  3. Open Convert Programming Files tool to generate the .pof file
Table 27.  Default Memory Map of the 512-Mb QSPI Flash
Block Description Size (KB) Address Range
Board test system scratch 512 0x03F8.0000 – 0x03FF.FFFF
User software 56640 0x0083.0000 – 0x03F7.FFFF
Factory software 4096 0x0043.0000 – 0x0082.FFFF
Zips(html, web content) 4096 0x0003.0000 – 0x0042.FFFF
Board information 64 0x0002.0000 – 0x0002.FFFF
Ethernet option bits 64 0x0001.0000 – 0x0001.FFFF
User design reset vector 64 0x0000.0000 – 0x0000.FFFF
Table 28.  Flash Pin Assignments, Schematic Signal Names, and Functions
Board Reference (U7) Schematic Signal Name Max 10 FPGA Pin Number I/O Standard Description
U7.7 QSPI_CSn C2 3.3V Chip select
U7.16 QSPI_CLK B2 3.3V Clock
U7.3 QSPI_RESETn W12 (MAX II) 3.3V Reset
U7.15 QSPI_IO0 C6 3.3V Address bus
U7.8 QSPI_IO1 C3 3.3V Address bus
U7.9 QSPI_IO2 C5 3.3V Address bus
U7.1 QSPI_IO3 B1 3.3V Address bus
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