MAX 10 FPGA Development Kit User Guide

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ID 683460
Date 9/07/2017
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Board Test System 4. Board Components A. Additional Information
1. Overview x
1.1. General Description 1.2. Handling the Board
2. Getting Started x
2.1. Quartus II Web Edition Software 2.2. Installing the Development Kit 2.3. Installing the USB-Blaster Driver 2.4. Board Update Portal
3. Board Test System x
3.1. Using the Configure Menu 3.2. The System Info Tab 3.3. The GPIO Tab 3.4. The Flash Tab 3.5. The HSMC Tab 3.6. The DDR3 Tab 3.7. The ADC Tab 3.8. The HDMI Tab 3.9. The Sleep Mode Tab 3.10. The Power Monitor 3.11. The Clock Control
4. Board Components x
4.1. Board Overview 4.2. Featured Device 4.3. Configuration 4.4. Status Elements 4.5. Setup Elements 4.6. General User Input/Output 4.7. Clock Circuitry 4.8. Components and Interfaces 4.9. Memory 4.10. Power Distribution System
4.3. Configuration x
4.3.1. Using the Quartus II Programmer 4.3.2. Selecting the Internal Configuration Scheme 4.3.3. Switch and Jumper Settings
4.7. Clock Circuitry x
4.7.1. On-Board Oscillators 4.7.2. Off-Board Clock Input/Output
4.8. Components and Interfaces x
4.8.1. 10/100/1000 Ethernet PHY 4.8.2. Digital-to-Analog Converter 4.8.3. HDMI Video Output 4.8.4. HSMC 4.8.5. Pmod Connectors 4.8.6. USB to UART
4.9. Memory x
4.9.1. DDR3 Rev. B Board 4.9.2. DDR3 Rev. C Board 4.9.3. Flash
A. Additional Information x
A.1. User Guide Revision History A.2. Compliance and Conformity Statements
A.2. Compliance and Conformity Statements x
A.2.1. CE EMI Conformity Caution
1. Overview
2. Getting Started
3. Board Test System
4. Board Components
A. Additional Information

4.8.5. Pmod Connectors

The MAX® 10 FPGA development kit features two Digilent Pmod™ compatible headers, which are used to connect low frequency, low I/O pin count peripheral modules.

The 12-pin version Pmod connector used in this kit provides 8 I/O signal pins. The peripheral module interface also encompasses a variant using I2C interface, and two or four wire MTE cables. The Pmod signals are connected to Bank 8.

Table 22.  Pmod A Pin Assignments, Signal Names and Functions
Schematic Signal Name Schematic Share Bus Signal Name MAX 10 FPGA Pin Number I/O Standard Description
PMODA_D0 PMODA_IO0 C7 3.3V In/Out
PMODA_D1 PMODA_IO1 C8 3.3V In/Out
PMODA_D2 PMODA_IO2 A6 3.3V In/Out
PMODA_D3 PMODA_IO3 B7 3.3V In/Out
PMODA_D4 PMODA_IO4 D8 3.3V In/Out
PMODA_D5 PMODA_IO5 A4 3.3V In/Out
PMODA_D6 PMODA_IO6 A5 3.3V In/Out
PMODA_D7 PMODA_IO7 E9 3.3V In/Out
— VCC — 3.3V Power
— GND — — GND
Table 23.  Pmod B Pin Assignments, Signal Names and Functions
Schematic Signal Name Schematic Share Bus Signal Name MAX 10 FPGA Pin Number I/O Standard Description
PMODB_D0 PMODB_IO0 E8 3.3V In/Out
PMODB_D1 PMODB_IO1 D5 3.3V In/Out
PMODB_D2 PMODB_IO2 B5 3.3V In/Out
PMODB_D3 PMODB_IO3 C4 3.3V In/Out
PMODB_D4 PMODB_IO4 A2 3.3V In/Out
PMODB_D5 PMODB_IO5 A3 3.3V In/Out
PMODB_D6 PMODB_IO6 B4 3.3V In/Out
PMODB_D7 PMODB_IO7 B3 3.3V In/Out
— VCC — 3.3V Power
— GND — — GND
Level Two Title