MAX 10 FPGA Development Kit User Guide

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ID 683460
Date 9/07/2017
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Board Test System 4. Board Components A. Additional Information
1. Overview x
1.1. General Description 1.2. Handling the Board
2. Getting Started x
2.1. Quartus II Web Edition Software 2.2. Installing the Development Kit 2.3. Installing the USB-Blaster Driver 2.4. Board Update Portal
3. Board Test System x
3.1. Using the Configure Menu 3.2. The System Info Tab 3.3. The GPIO Tab 3.4. The Flash Tab 3.5. The HSMC Tab 3.6. The DDR3 Tab 3.7. The ADC Tab 3.8. The HDMI Tab 3.9. The Sleep Mode Tab 3.10. The Power Monitor 3.11. The Clock Control
4. Board Components x
4.1. Board Overview 4.2. Featured Device 4.3. Configuration 4.4. Status Elements 4.5. Setup Elements 4.6. General User Input/Output 4.7. Clock Circuitry 4.8. Components and Interfaces 4.9. Memory 4.10. Power Distribution System
4.3. Configuration x
4.3.1. Using the Quartus II Programmer 4.3.2. Selecting the Internal Configuration Scheme 4.3.3. Switch and Jumper Settings
4.7. Clock Circuitry x
4.7.1. On-Board Oscillators 4.7.2. Off-Board Clock Input/Output
4.8. Components and Interfaces x
4.8.1. 10/100/1000 Ethernet PHY 4.8.2. Digital-to-Analog Converter 4.8.3. HDMI Video Output 4.8.4. HSMC 4.8.5. Pmod Connectors 4.8.6. USB to UART
4.9. Memory x
4.9.1. DDR3 Rev. B Board 4.9.2. DDR3 Rev. C Board 4.9.3. Flash
A. Additional Information x
A.1. User Guide Revision History A.2. Compliance and Conformity Statements
A.2. Compliance and Conformity Statements x
A.2.1. CE EMI Conformity Caution
1. Overview
2. Getting Started
3. Board Test System
4. Board Components
A. Additional Information

4.8.3. HDMI Video Output

The MAX 10 FPGA development kit supports one HDMI transmitter and one HDMI receptacle.

The transmitter incorporates HDMI v1.4 features, and is capable of supporting an input data rate up to 165 MHz (1080p @60Hz, UXGA @60Hz). The connection between HDMI transmitter and MAX 10 is established in Bank 7, and the communication can be done via I2C interface.

Table 20.  HDMI Pin Assignments, Signal Names and Functions
Board Reference (U8) Schematic Signal Name Max 10 FPGA Pin Number I/O Standard Description
U8.62 HDMI_TX_D0 A17 3.3 V HDMI digital video data bus
U8.61 HDMI_TX_D1 A18 3.3 V HDMI digital video data bus
U8.60 HDMI_TX_D2 A12 3.3 V HDMI digital video data bus
U8.59 HDMI_TX_D3 F16 3.3 V HDMI digital video data bus
U8.58 HDMI_TX_D4 A16 3.3 V HDMI digital video data bus
U8.57 HDMI_TX_D5 B12 3.3 V HDMI digital video data bus
U8.56 HDMI_TX_D6 F15 3.3 V HDMI digital video data bus
U8.55 HDMI_TX_D7 B11 3.3 V HDMI digital video data bus
U8.54 HDMI_TX_D8 A13 3.3 V HDMI digital video data bus
U8.52 HDMI_TX_D9 C15 3.3 V HDMI digital video data bus
U8.50 HDMI_TX_D10 C11 3.3 V HDMI digital video data bus
U8.49 HDMI_TX_D11 A11 3.3 V HDMI digital video data bus
U8.48 HDMI_TX_D12 A20 3.3 V HDMI digital video data bus
U8.47 HDMI_TX_D13 H13 3.3 V HDMI digital video data bus
U8.46 HDMI_TX_D14 E14 3.3 V HDMI digital video data bus
U8.45 HDMI_TX_D15 D12 3.3 V HDMI digital video data bus
U8.44 HDMI_TX_D16 C12 3.3 V HDMI digital video data bus
U8.43 HDMI_TX_D17 C19 3.3 V HDMI digital video data bus
U8.42 HDMI_TX_D18 C18 3.3 V HDMI digital video data bus
U8.41 HDMI_TX_D19 B19 3.3 V HDMI digital video data bus
U8.40 HDMI_TX_D20 B17 3.3 V HDMI digital video data bus
U8.39 HDMI_TX_D21 B16 3.3 V HDMI digital video data bus
U8.38 HDMI_TX_D22 C16 3.3 V HDMI digital video data bus
U8.37 HDMI_TX_D23 A15 3.3 V HDMI digital video data bus
U8.53 HDMI_TX_CLK D6 3.3 V Video clock
U8.63 HDMI_TX_DE C10 3.3 V Video data enable
U8.64 HDMI_TX_HS A19 3.3 V Vertical Synchronization
U8.2 HDMI_TX_VS J12 3.3 V Horizontal Synchronization
U8.28 HDMI_TX_INT D15 3.3 V Interrupt Signal
U8.35 HDMI_SCL A10 3.3 V HDMI I2C clock
U8.36 HDMI_SDA B15 3.3 V HDMI I2C data
Level Two Title