MAX 10 FPGA Development Kit User Guide

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ID 683460
Date 9/07/2017
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Board Test System 4. Board Components A. Additional Information
1. Overview x
1.1. General Description 1.2. Handling the Board
2. Getting Started x
2.1. Quartus II Web Edition Software 2.2. Installing the Development Kit 2.3. Installing the USB-Blaster Driver 2.4. Board Update Portal
3. Board Test System x
3.1. Using the Configure Menu 3.2. The System Info Tab 3.3. The GPIO Tab 3.4. The Flash Tab 3.5. The HSMC Tab 3.6. The DDR3 Tab 3.7. The ADC Tab 3.8. The HDMI Tab 3.9. The Sleep Mode Tab 3.10. The Power Monitor 3.11. The Clock Control
4. Board Components x
4.1. Board Overview 4.2. Featured Device 4.3. Configuration 4.4. Status Elements 4.5. Setup Elements 4.6. General User Input/Output 4.7. Clock Circuitry 4.8. Components and Interfaces 4.9. Memory 4.10. Power Distribution System
4.3. Configuration x
4.3.1. Using the Quartus II Programmer 4.3.2. Selecting the Internal Configuration Scheme 4.3.3. Switch and Jumper Settings
4.7. Clock Circuitry x
4.7.1. On-Board Oscillators 4.7.2. Off-Board Clock Input/Output
4.8. Components and Interfaces x
4.8.1. 10/100/1000 Ethernet PHY 4.8.2. Digital-to-Analog Converter 4.8.3. HDMI Video Output 4.8.4. HSMC 4.8.5. Pmod Connectors 4.8.6. USB to UART
4.9. Memory x
4.9.1. DDR3 Rev. B Board 4.9.2. DDR3 Rev. C Board 4.9.3. Flash
A. Additional Information x
A.1. User Guide Revision History A.2. Compliance and Conformity Statements
A.2. Compliance and Conformity Statements x
A.2.1. CE EMI Conformity Caution
1. Overview
2. Getting Started
3. Board Test System
4. Board Components
A. Additional Information

4.6. General User Input/Output

User-defined I/O signal names, FPGA pin numbers, and I/O standards for the MAX® 10 FPGA development board.
Table 11.  User-Defined Push Button Signal Names
Board Reference Signal Name

MAX 10 FPGA

Pin Number

 I/O Standard
S1 USER_PB0 L22 1.5 V
S2 USER_PB1 M21 1.5 V
S3 USER_PB2 M22 1.5 V
S4 USER_PB3 N21 1.5 V
Table 12.  User-Defined DIP Switch Schematic Signal Names
Board Reference Signal Name

MAX 10 FPGA

Pin Number

 I/O Standard
SW1.1 USER_DIPSW0 H21 1.5 V
SW1.2 USER_DIPSW1 H22 1.5 V
SW1.3 USER_DIPSW2 J21 1.5 V
SW1.4 USER_DIPSW3 J22 1.5 V
SW2.1 USER_DIPSW4 G19 1.5 V
Table 13.  User LED (Green) Schematic Signal Names
Board Reference Signal Name

MAX 10 FPGA

Pin Number

 I/O Standard
D15 USER_LED0 T20 1.5 V
D16 USER_LED1 U22 1.5 V
D17 USER_LED2 U21 1.5 V
D18 USER_LED3 AA21 1.5 V
D19 USER_LED4 AA22 1.5 V
For a MAX 10 Development Kit Baseline Pinout design vist the Altera Design Store.
Related Information
Level Two Title