MAX 10 FPGA Development Kit User Guide

Download PDF
ID 683460
Date 9/07/2017
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Board Test System 4. Board Components A. Additional Information
1. Overview x
1.1. General Description 1.2. Handling the Board
2. Getting Started x
2.1. Quartus II Web Edition Software 2.2. Installing the Development Kit 2.3. Installing the USB-Blaster Driver 2.4. Board Update Portal
3. Board Test System x
3.1. Using the Configure Menu 3.2. The System Info Tab 3.3. The GPIO Tab 3.4. The Flash Tab 3.5. The HSMC Tab 3.6. The DDR3 Tab 3.7. The ADC Tab 3.8. The HDMI Tab 3.9. The Sleep Mode Tab 3.10. The Power Monitor 3.11. The Clock Control
4. Board Components x
4.1. Board Overview 4.2. Featured Device 4.3. Configuration 4.4. Status Elements 4.5. Setup Elements 4.6. General User Input/Output 4.7. Clock Circuitry 4.8. Components and Interfaces 4.9. Memory 4.10. Power Distribution System
4.3. Configuration x
4.3.1. Using the Quartus II Programmer 4.3.2. Selecting the Internal Configuration Scheme 4.3.3. Switch and Jumper Settings
4.7. Clock Circuitry x
4.7.1. On-Board Oscillators 4.7.2. Off-Board Clock Input/Output
4.8. Components and Interfaces x
4.8.1. 10/100/1000 Ethernet PHY 4.8.2. Digital-to-Analog Converter 4.8.3. HDMI Video Output 4.8.4. HSMC 4.8.5. Pmod Connectors 4.8.6. USB to UART
4.9. Memory x
4.9.1. DDR3 Rev. B Board 4.9.2. DDR3 Rev. C Board 4.9.3. Flash
A. Additional Information x
A.1. User Guide Revision History A.2. Compliance and Conformity Statements
A.2. Compliance and Conformity Statements x
A.2.1. CE EMI Conformity Caution
1. Overview
2. Getting Started
3. Board Test System
4. Board Components
A. Additional Information

4.9.1. DDR3 Rev. B Board

Note: For your board's revision, look for the board serial number on the back of the board at the bottom. Refer to the General Description section for an image of the back board.
The MAX® 10 FPGA provides full-speed support to a x16 DDR3 300-MHz interface by using a 1 Gbit x16 memory. Additionally, the MAX 10 supports the error correction code (ECC) feature.
CAUTION:
The DDR3 address signals at F18, E19, F20 and F21 on rev. B boards violate MAX 10 external memory guidelines when implementing DDR3 on the 10M50 F484 device. Altera recommends you follow the MAX 10 guidelines for your own board designs and utilize Quartus II software to verify pin location compliance. Contact Altera support if you received DDR3 pin location errors for your Rev. B kit designs.
Table 25.  DDR3 Pin Assignments, Signal Names, and Functions
Board Reference (U5 & U6) Schematic Signal Name MAX 10 FPGA Pin Number I/O Standard Description
U5.N3 - U6.K3 DDR3_A0 V20 1.5V SSTL Address bus
U5.P7 - U6.L7 DDR3_A1 F20 1.5V SSTL

Address bus

Refer to Caution statement above.

U5.P3 - U6.L3 DDR3_A2 F18 1.5V SSTL

Address bus

Refer to Caution statement above.

U5.N2 - U6.K2 DDR3_A3 U20 1.5V SSTL Address bus
U5.P8 - U6.L8 DDR3_A4 F21 1.5V SSTL

Address bus

Refer to Caution statement above.

U5.P2 - U6.L2 DDR3_A5 F19 1.5V SSTL Address bus
U5.R8 - U6.M8 DDR3_A6 E21 1.5V SSTL Address bus
U5.R2 -U6.M2 DDR3_A7 E19 1.5V SSTL

Address bus

Refer to Caution statement above.

U5.T8 - U6.N8 DDR3_A8 D22 1.5V SSTL Address bus
U5.R3 - U6.M3 DDR3_A9 E22 1.5V SSTL Address bus
U5.L7 - U6.H7 DDR3_A10 Y20 1.5V SSTL Address bus
U5.R7 - U6.M7 DDR3_A11 E20 1.5V SSTL Address bus
U5.N7 - U6.K7 DDR3_A12 J14 1.5V SSTL Address bus
U5.T3 - U6.N3 DDR3_A13 C22 1.5V SSTL Address bus
U5.M2 - U6.J2 DDR3_BA0 V22 1.5V SSTL Bank address bus
U5.N8 - U6.K8 DDR3_BA1 N18 1.5V SSTL Bank address bus
U5.M3 - U6.J3 DDR3_BA2 W22 1.5V SSTL Bank address bus
U5.K3 - U6.G3 DDR3_CASn U19 1.5V SSTL Row address bus
U5.K9 - U6.G9 DDR3_CKE W20 1.5V SSTL Clock enable
U5.J7 - U6.F7 DDR3_CLK_P D18 Differential 1.5V SSTL Differential output clock
U5.K7 - U6.G7 DDR3_CLK_N E18 Differential 1.5V SSTL Differential output clock
U5.L2 - U6.H2 DDR3_CSn Y22 1.5V SSTL Chip select
U5.E7 DDR3_DM0 J15 1.5V SSTL Write mask byte lane 0
U5.D3 DDR3_DM1 N19 1.5V SSTL Write mask byte lane 1
U6.B7 DDR3_DM2 T18 1.5V SSTL Write mask byte lane 2
U5.E3 DDR3_DQ0 J18 1.5V SSTL Data bus byte lane 0
U5.F7 DDR3_DQ1 K20 1.5V SSTL Data bus byte lane 0
U5.F2 DDR3_DQ2 H18 1.5V SSTL Data bus byte lane 0
U5.F8 DDR3_DQ3 K18 1.5V SSTL Data bus byte lane 0
U5.H3 DDR3_DQ4 H19 1.5V SSTL Data bus byte lane 0
U5.H8 DDR3_DQ5 J20 1.5V SSTL Data bus byte lane 0
U5.G2 DDR3_DQ6 H20 1.5V SSTL Data bus byte lane 0
U5.H7 DDR3_DQ7 K19 1.5V SSTL Data bus byte lane 0
U5.D7 DDR3_DQ8 L20 1.5V SSTL Data bus byte lane 1
U5.C3 DDR3_DQ9 M18 1.5V SSTL Data bus byte lane 1
U5.C8 DDR3_DQ10 M20 1.5V SSTL Data bus byte lane 1
U5.C2 DDR3_DQ11 M14 1.5V SSTL Data bus byte lane 1
U5.A7 DDR3_DQ12 L18 1.5V SSTL Data bus byte lane 1
U5.A2 DDR3_DQ13 M15 1.5V SSTL Data bus byte lane 1
U5.B8 DDR3_DQ14 L19 1.5V SSTL Data bus byte lane 1
U5.A3 DDR3_DQ15 N20 1.5V SSTL Data bus byte lane 1
U6.B3 DDR3_DQ16 R14 1.5V SSTL Data bus byte lane 2
U6.C7 DDR3_DQ17 P19 1.5V SSTL Data bus byte lane 2
U6.C2 DDR3_DQ18 P14 1.5V SSTL Data bus byte lane 2
U6.C8 DDR3_DQ19 R20 1.5V SSTL Data bus byte lane 2
U6.E3 DDR3_DQ20 R15 1.5V SSTL Data bus byte lane 2
U6.E8 DDR3_DQ21 T19 1.5V SSTL Data bus byte lane 2
U6.D2 DDR3_DQ22 P15 1.5V SSTL Data bus byte lane 2
U6.E7 DDR3_DQ23 P20 1.5V SSTL Data bus byte lane 2
U5.F3 DDR3_DQS_P0 K14 Differential 1.5V SSTL Data strobe P byte lane 0
U5.G3 DDR3_DQS_N0 K15 Differential 1.5V SSTL Data strobe N byte lane 0
U5.C7 DDR3_DQS_P1 L14 Differential 1.5V SSTL Data strobe P byte lane 1
U5.B7 DDR3_DQS_N1 L15 Differential 1.5V SSTL Data strobe N byte lane 1
U6.C3 DDR3_DQS_P2 R18 Differential 1.5V SSTL Data strobe P byte lane 2
U6.D3 DDR3_DQS_N2 P18 Differential 1.5V SSTL Data strobe N byte lane 2
U5.K1 - U6.G1 DDR3_ODT W19 1.5V SSTL On-die termination enable
U5.J3 - U6.F3 DDR3_RASn V18 1.5V SSTL Row address select
U5.T2 - U6.N2 DDR3_RESETn B22 1.5V SSTL Reset
U5.L3 - U6.H3 DDR3_WEn Y21 1.5V SSTL Write enable
U5.L8 DDR3_ZQ1 — 1.5V SSTL ZQ impedance calibration
U6.H8 DDR3_ZQ2 — 1.5V SSTL ZQ impedance calibration
Related Information
Level Two Title