MAX 10 FPGA Development Kit User Guide

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ID 683460
Date 9/07/2017
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Board Test System 4. Board Components A. Additional Information
1. Overview x
1.1. General Description 1.2. Handling the Board
2. Getting Started x
2.1. Quartus II Web Edition Software 2.2. Installing the Development Kit 2.3. Installing the USB-Blaster Driver 2.4. Board Update Portal
3. Board Test System x
3.1. Using the Configure Menu 3.2. The System Info Tab 3.3. The GPIO Tab 3.4. The Flash Tab 3.5. The HSMC Tab 3.6. The DDR3 Tab 3.7. The ADC Tab 3.8. The HDMI Tab 3.9. The Sleep Mode Tab 3.10. The Power Monitor 3.11. The Clock Control
4. Board Components x
4.1. Board Overview 4.2. Featured Device 4.3. Configuration 4.4. Status Elements 4.5. Setup Elements 4.6. General User Input/Output 4.7. Clock Circuitry 4.8. Components and Interfaces 4.9. Memory 4.10. Power Distribution System
4.3. Configuration x
4.3.1. Using the Quartus II Programmer 4.3.2. Selecting the Internal Configuration Scheme 4.3.3. Switch and Jumper Settings
4.7. Clock Circuitry x
4.7.1. On-Board Oscillators 4.7.2. Off-Board Clock Input/Output
4.8. Components and Interfaces x
4.8.1. 10/100/1000 Ethernet PHY 4.8.2. Digital-to-Analog Converter 4.8.3. HDMI Video Output 4.8.4. HSMC 4.8.5. Pmod Connectors 4.8.6. USB to UART
4.9. Memory x
4.9.1. DDR3 Rev. B Board 4.9.2. DDR3 Rev. C Board 4.9.3. Flash
A. Additional Information x
A.1. User Guide Revision History A.2. Compliance and Conformity Statements
A.2. Compliance and Conformity Statements x
A.2.1. CE EMI Conformity Caution
1. Overview
2. Getting Started
3. Board Test System
4. Board Components
A. Additional Information

4.7.1. On-Board Oscillators

Figure 20. MAX 10 FPGA Development Board Clocks
Table 14.  On-Board Oscillators
Source Schematic Signal Name Frequency I/O Standard MAX 10 FPGA Pin Number Application
X1

CLK_10_ADC

 10.000 MHz 2.5 V CMOS N5 Programmable default 10MHz clock for ADC
U2

CLK_25_ENET

 25.000 MHz 2.5 V CMOS - Ethernet clock
U2 CLK_25_MAX10 25.000 MHz 2.5 V CMOS M8 MAX 10 clock
U2 CLK_50_MAXII 25.000 MHz 2.5 V/3.3V CMOS - Clock for On-Board USB Blaster II
U2

CLK_50_MAX10

 50.000 MHz 2.5 V CMOS M9 MAX 10 clock
U2

CLK_DDR3_100_N

 100.000 MHz Differential SSTL-15 N15 DDR3 clocks
U2

CLK_DDR3_100_P

 100.000 MHz Differential SSTL-15 N14 DDR3 clocks
U2

CLK_LVDS_125_N

 125.000 MHz 2.5 V LVDS R11 LVDS clocks
U2

CLK_LVDS_125_P

 125.000 MHz 2.5 V LVDS P11 LVDS clocks
Note: For signal CLK_50_MAXII, the output side voltage is 2.5V and the input side voltage is 3.3V. However, they are compatible electrically.
Note: For signals CLK_DDR3_100_P and CLK_DDR3_100_N, at the MAX 10 input side, Differential SSTL-15 is used as I/O standard because this bank's VCCIO is 1.5V.
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