External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs

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ID 817467
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the External Memory Interfaces Agilex™ 5 FPGA IP 2. Agilex™ 5 FPGA EMIF IP – Introduction 3. Agilex™ 5 FPGA EMIF IP – Product Architecture 4. Agilex™ 5 FPGA EMIF IP – End-User Signals 5. Agilex™ 5 FPGA EMIF IP – Simulating Memory IP 6. Intel® Agilex™ 5 FPGA EMIF IP - DDR4 Support 7. Intel® Agilex™ 5 FPGA EMIF IP - LPDDR4 Support 8. Intel® Agilex™ 5 FPGA EMIF IP - LPDDR5 Support 9. Agilex™ 5 FPGA EMIF IP – Timing Closure 10. Agilex™ 5 FPGA EMIF IP – Controller Optimization 11. Agilex™ 5 FPGA EMIF IP – Debugging 12. Document Revision History for External Memory Interfaces (EMIF) IP User Guide
1. About the External Memory Interfaces Agilex™ 5 FPGA IP x
1.1. Release Information
2. Agilex™ 5 FPGA EMIF IP – Introduction x
2.1. Agilex™ 5 EMIF IP Protocol and Feature Support 2.2. Agilex™ 5 EMIF IP Design Flow
2.2. Agilex™ 5 EMIF IP Design Flow x
2.2.1. Agilex™ 5 EMIF IP Design Checklist
3. Agilex™ 5 FPGA EMIF IP – Product Architecture x
3.1. Agilex™ 5 EMIF Architecture: Protocol and Maximum Interface Width Support 3.2. Agilex™ 5 EMIF Architecture: Introduction 3.3. Agilex™ 5 EMIF Sequencer 3.4. Agilex™ 5 EMIF Controller 3.5. Agilex™ 5 EMIF IP for Hard Processor Subsystem (HPS)
3.2. Agilex™ 5 EMIF Architecture: Introduction x
3.2.1. Agilex™ 5 EMIF Architecture: I/O Subsystem 3.2.2. Agilex™ 5 EMIF Architecture: I/O SSM 3.2.3. Agilex™ 5 EMIF Architecture: HSIO Bank 3.2.4. Agilex™ 5 EMIF Architecture: I/O Lane 3.2.5. Agilex™ 5 EMIF Architecture: Input DQS Clock Tree 3.2.6. Agilex™ 5 EMIF Architecture: PHY Clock Tree 3.2.7. Agilex™ 5 EMIF Architecture: PLL Reference Clock Networks 3.2.8. Agilex™ 5 EMIF Architecture: Clock Phase Alignment 3.2.9. User Clock in Different Core Access Modes
3.2.3. Agilex™ 5 EMIF Architecture: HSIO Bank x
3.2.3.1. Pin Placement 3.2.3.2. HSIO Sub-Bank Usage
3.3. Agilex™ 5 EMIF Sequencer x
3.3.1. Agilex™ 5 Mailbox Structure and Register Definitions
3.3.1. Agilex™ 5 Mailbox Structure and Register Definitions x
3.3.1.1. Mailbox Supported Commands 3.3.1.2. Mailbox Command Definitions
3.4. Agilex™ 5 EMIF Controller x
3.4.1. Hard Memory Controller
3.4.1. Hard Memory Controller x
3.4.1.1. Hard Memory Controller Features
4. Agilex™ 5 FPGA EMIF IP – End-User Signals x
4.1. Agilex™ 5 FPGA EMIF IP Interfaces for DDR4 4.2. Agilex™ 5 FPGA EMIF IP Interfaces for LPDDR4 4.3. Agilex™ 5 FPGA EMIF IP Interfaces for LPDDR5 4.4. Agilex™ 5 FPGA EMIF IP Interfaces for EMIF Calibration Component
4.1. Agilex™ 5 FPGA EMIF IP Interfaces for DDR4 x
4.1.1. ref_clk for EMIF 4.1.2. core_init_n for EMIF 4.1.3. usr_async_clk for EMIF 4.1.4. usr_clk for EMIF 4.1.5. usr_rst_n for EMIF 4.1.6. s0_axi4 for EMIF 4.1.7. mem for EMIF 4.1.8. oct for EMIF
4.2. Agilex™ 5 FPGA EMIF IP Interfaces for LPDDR4 x
4.2.1. ref_clk for EMIF 4.2.2. core_init_n for EMIF 4.2.3. usr_async_clk for EMIF 4.2.4. usr_clk for EMIF 4.2.5. usr_rst_n for EMIF 4.2.6. s0_axi4 for EMIF 4.2.7. mem for EMIF 4.2.8. oct for EMIF
4.3. Agilex™ 5 FPGA EMIF IP Interfaces for LPDDR5 x
4.3.1. ref_clk for EMIF 4.3.2. core_init_n for EMIF 4.3.3. usr_async_clk for EMIF 4.3.4. usr_clk for EMIF 4.3.5. usr_rst_n for EMIF 4.3.6. s0_axi4 for EMIF 4.3.7. oct for EMIF
4.4. Agilex™ 5 FPGA EMIF IP Interfaces for EMIF Calibration Component x
4.4.1. s0_axi4lite_clk for EMIF 4.4.2. s0_axi4lite_rst_n for EMIF 4.4.3. s0_axil for EMIF
5. Agilex™ 5 FPGA EMIF IP – Simulating Memory IP x
5.1. Simulation Walkthrough
5.1. Simulation Walkthrough x
5.1.1. Calibration 5.1.2. Simulation Scripts 5.1.3. Functional Simulation with Verilog HDL 5.1.4. Simulating the Design Example
6. Intel® Agilex™ 5 FPGA EMIF IP - DDR4 Support x
6.1. Intel® Agilex™ 5 FPGA EMIF IP Parameters for DDR4 6.2. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning 6.3. Agilex™ 5 EMIF Pin Swapping Guidelines 6.4. DDR4 Layout Design Guidelines
6.1. Intel® Agilex™ 5 FPGA EMIF IP Parameters for DDR4 x
6.1.1. Agilex™ 5 FPGA EMIF IP Parameter for DDR4 6.1.2. Intel Agilex 5 FPGA EMIF Memory Device Description IP (DDR4) Parameter Descriptions
6.2. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning x
6.2.1. Intel® Agilex™ 5 FPGA EMIF IP Resources 6.2.2. Pin Guidelines for Intel® Agilex™ 5 FPGA EMIF IP 6.2.3. Pin Placements for Intel® Agilex™ 5 FPGA DDR4 EMIF IP
6.2.1. Intel® Agilex™ 5 FPGA EMIF IP Resources x
6.2.1.1. OCT 6.2.1.2. PLL
6.2.2. Pin Guidelines for Intel® Agilex™ 5 FPGA EMIF IP x
6.2.2.1. Intel® Agilex™ 5 FPGA EMIF IP Pin and Resource Planning
6.2.2.1. Intel® Agilex™ 5 FPGA EMIF IP Pin and Resource Planning x
6.2.2.1.1. Intel® Agilex™ 5 FPGA EMIF IP Interface Pins 6.2.2.1.2. Estimating Pin Requirements 6.2.2.1.3. Maximum Number of Interfaces
6.2.3. Pin Placements for Intel® Agilex™ 5 FPGA DDR4 EMIF IP x
6.2.3.1. Address and Command Pin Placement for DDR4 6.2.3.2. DDR4 Data Width Mapping 6.2.3.3. General Guidelines 6.2.3.4. Specific Pin Connection Requirements 6.2.3.5. Command and Address Signals 6.2.3.6. Clock Signals 6.2.3.7. Data, Data Strobes, DM/DBI, and Optional ECC Signals
6.3. Agilex™ 5 EMIF Pin Swapping Guidelines x
6.3.1. DDR4 Byte Lane Swapping 6.3.2. DDR4 Address and Command and CLK Lane 6.3.3. DDR4 Interface x8 Data Lane 6.3.4. DDR4 Interface x4 Data Lane
6.4. DDR4 Layout Design Guidelines x
6.4.1. DDR4 PCB Stackup and Design Considerations 6.4.2. DDR4 General Design Considerations 6.4.3. DDR4 Routing Guidelines - Memory-Down (Discrete) Topologies
6.4.3. DDR4 Routing Guidelines - Memory-Down (Discrete) Topologies x
6.4.3.1. 1 Rank x 8 Discrete (Memory Down) Topology 6.4.3.2. 1 Rank x 16 Discrete (Memory Down) Topology 6.4.3.3. VREF_CA/RESET Signal Routing Guidelines for 1 Rank x 8 and 1 Rank x 16 Discrete (Memory Down) Topology 6.4.3.4. Skew Matching Guidelines for DDR4 (Memory Down) Discrete Configurations 6.4.3.5. Power Delivery Recommendation for DDR4 Discrete Configurations 6.4.3.6. DDR4 Simulation Strategy
7. Intel® Agilex™ 5 FPGA EMIF IP - LPDDR4 Support x
7.1. Intel® Agilex™ 5 FPGA EMIF IP Parameters for LPDDR4 7.2. Intel® Agilex™ 5 FPGA EMIF IP Pin and Resource Planning 7.3. LPDDR4 Layout Design Guidelines
7.1. Intel® Agilex™ 5 FPGA EMIF IP Parameters for LPDDR4 x
7.1.1. Agilex™ 5 FPGA EMIF IP Parameter for LPDDR4 7.1.2. Intel Agilex 5 FPGA EMIF Memory Device Description IP (LPDDR4) Parameter Descriptions
7.2. Intel® Agilex™ 5 FPGA EMIF IP Pin and Resource Planning x
7.2.1. Intel® Agilex™ 5 FPGA EMIF IP Interface Pins 7.2.2. Intel® Agilex™ 5 FPGA EMIF IP Resources 7.2.3. Pin Guidelines for Intel® Agilex™ 5 FPGA EMIF IP
7.2.1. Intel® Agilex™ 5 FPGA EMIF IP Interface Pins x
7.2.1.1. Estimating Pin Requirements 7.2.1.2. LPDDR4 Component Options 7.2.1.3. Maximum Number of Interfaces
7.2.2. Intel® Agilex™ 5 FPGA EMIF IP Resources x
7.2.2.1. OCT 7.2.2.2. PLL
7.2.3. Pin Guidelines for Intel® Agilex™ 5 FPGA EMIF IP x
7.2.3.1. General Guidelines 7.2.3.2. Specific Pin Connection Requirements 7.2.3.3. Command and Address Signals 7.2.3.4. Clock Signals 7.2.3.5. Address and Command Pin Placement for LPDDR4 7.2.3.6. Pin Placements for Agilex™ 5 FPGA EMIF IP for LPDDR4 7.2.3.7. Pin Swapping Guidelines
7.3. LPDDR4 Layout Design Guidelines x
7.3.1. LPDDR4 PCB Stackup and Design Considerations 7.3.2. LPDDR4 General Design Considerations 7.3.3. LPDDR4 Interface Design Guidelines
7.3.3. LPDDR4 Interface Design Guidelines x
7.3.3.1. LPDDR4 Discrete Component/Memory Down Topology (up to 32 bits interface) 7.3.3.2. LPDDR4 Simulation Strategy
8. Intel® Agilex™ 5 FPGA EMIF IP - LPDDR5 Support x
8.1. Intel Agilex 5 FPGA EMIF IP Parameters for LPDDR5 8.2. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning 8.3. LPDDR5 Layout Design Guidelines
8.1. Intel Agilex 5 FPGA EMIF IP Parameters for LPDDR5 x
8.1.1. Agilex™ 5 FPGA EMIF IP Parameter for LPDDR5 8.1.2. Intel Agilex 5 FPGA EMIF Memory Device Description IP (LPDDR5) Parameter Descriptions
8.2. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning x
8.2.1. Agilex™ 5 FPGA EMIF IP Interface Pins 8.2.2. Agilex™ 5 FPGA EMIF IP Resources 8.2.3. Pin Guidelines for Agilex™ 5 FPGA EMIF IP 8.2.4. Pin Placements for Intel Agilex 5 FPGA LPDDR5 EMIF IP
8.2.1. Agilex™ 5 FPGA EMIF IP Interface Pins x
8.2.1.1. Estimating Pin Requirements 8.2.1.2. LPDDR5 Component Options 8.2.1.3. Maximum Number of Interfaces
8.2.2. Agilex™ 5 FPGA EMIF IP Resources x
8.2.2.1. OCT 8.2.2.2. PLL
8.2.3. Pin Guidelines for Agilex™ 5 FPGA EMIF IP x
8.2.3.1. General Guidelines - LPDDR5 8.2.3.2. Specific Pin Connection Requirements 8.2.3.3. Command and Address Signals 8.2.3.4. Clock Signals
8.2.4. Pin Placements for Intel Agilex 5 FPGA LPDDR5 EMIF IP x
8.2.4.1. Address and Command Pin Placement for LPDDR5 8.2.4.2. LPDDR5 Data Width Mapping 8.2.4.3. LPDDR5 Byte Lane Swapping
8.3. LPDDR5 Layout Design Guidelines x
8.3.1. LPDDR5 PCB Stackup and Design Considerations 8.3.2. LPDDR5 General Design Considerations 8.3.3. LPDDR5 Interface Design Guidelines
8.3.3. LPDDR5 Interface Design Guidelines x
8.3.3.1. LPDDR5 Discrete Component/Memory Down Topology (Single Rank or Dual-Rank) 8.3.3.2. Example of an LPDDR5 Layout on an Intel FPGA Platform Board 8.3.3.3. LPDDR5 Simulation Strategy
9. Agilex™ 5 FPGA EMIF IP – Timing Closure x
9.1. Timing Closure 9.2. Optimizing Timing
9.1. Timing Closure x
9.1.1. Timing Analysis
9.1.1. Timing Analysis x
9.1.1.1. PHY or Core
10. Agilex™ 5 FPGA EMIF IP – Controller Optimization x
10.1. Interface Standard 10.2. Bank Management Efficiency 10.3. Data Transfer 10.4. Improving Controller Efficiency
10.4. Improving Controller Efficiency x
10.4.1. Frequency of Operation 10.4.2. Series of Reads or Writes
11. Agilex™ 5 FPGA EMIF IP – Debugging x
11.1. Interface Configuration Performance Issues 11.2. Functional Issue Evaluation 11.3. Timing Issue Characteristics 11.4. Verifying Memory IP Using the Signal Tap Logic Analyzer 11.5. Generating Traffic with the Test Engine IP 11.6. Guidelines for Developing HDL for Traffic Generator 11.7. Hardware Debugging Guidelines 11.8. Create a Simplified Design that Demonstrates the Same Issue 11.9. Measure Power Distribution Network 11.10. Measure Signal Integrity and Setup and Hold Margin 11.11. Vary Voltage 11.12. Operate at a Lower Speed 11.13. Determine Whether the Issue Exists in Previous Versions of Software 11.14. Determine Whether the Issue Exists in the Current Version of Software 11.15. Try A Different PCB 11.16. Try Other Configurations 11.17. Debugging Checklist 11.18. Categorizing Hardware Issues 11.19. Signal Integrity Issues 11.20. Characteristics of Signal Integrity Issues 11.21. Evaluating Signal Integrity Issues 11.22. Skew 11.23. Crosstalk 11.24. Power System 11.25. Clock Signals 11.26. Address and Command Signals 11.27. Read Data Valid Window and Eye Diagram 11.28. Write Data Valid Window and Eye Diagram 11.29. Hardware and Calibration Issues 11.30. Memory Timing Parameter Evaluation 11.31. Verify that the Board Has the Correct Memory Component or DIMM Installed
11.1. Interface Configuration Performance Issues x
11.1.1. Interface Configuration Bottleneck and Efficiency Issues
11.2. Functional Issue Evaluation x
11.2.1. Intel® IP Memory Model 11.2.2. Vendor Memory Model 11.2.3. Transcript Window Messages
11.3. Timing Issue Characteristics x
11.3.1. Evaluating FPGA Timing Issues 11.3.2. Evaluating External Memory Interface Timing Issues
1. About the External Memory Interfaces Agilex™ 5 FPGA IP
2. Agilex™ 5 FPGA EMIF IP – Introduction
3. Agilex™ 5 FPGA EMIF IP – Product Architecture
4. Agilex™ 5 FPGA EMIF IP – End-User Signals
5. Agilex™ 5 FPGA EMIF IP – Simulating Memory IP
6. Intel® Agilex™ 5 FPGA EMIF IP - DDR4 Support
7. Intel® Agilex™ 5 FPGA EMIF IP - LPDDR4 Support
8. Intel® Agilex™ 5 FPGA EMIF IP - LPDDR5 Support
9. Agilex™ 5 FPGA EMIF IP – Timing Closure
10. Agilex™ 5 FPGA EMIF IP – Controller Optimization
11. Agilex™ 5 FPGA EMIF IP – Debugging
12. Document Revision History for External Memory Interfaces (EMIF) IP User Guide

8.3.3.1. LPDDR5 Discrete Component/Memory Down Topology (Single Rank or Dual-Rank)

LPDDR5 memory down support is available in two configurations: single rank or dual–rank.

There are four DRAM interface signal groupings: data group, command-address group, control group, and clock group. The FPGA to DRAM connection uses point-to-point topology for data group, command-address group, control group, and clock group. The figure below shows the stripline routing topology for inner pins.

Figure 54. Stripline Routing Topology for Data, CA, CTRL and Clock Signals Point-to-Point Topology

The figure below shows the microstrip routing for the edge pins per byte.

Figure 55. Microstrip Routing Topology for Data Signals Point-to-Point Topology

LPDDR5 interfaces do not support traditional dual-directional data-strobe architecture; however, two single-directional data strobes such as Write Clock (WCK) for write operations and an optional Read Clock (RDQS) for read operations are added. The following two figures show the T-Line connection topology for WCK signal and CA, CLK, CTRL signals.

The figure below shows the stripline routing topology for inner pins.

Figure 56. Stripline Routing for WCK Signals T-Line Topology

The figure below show the daisy or T-Line connection topology for CA, CLK, and CTRL signals.

Figure 57. Stripline Routing for CA, CLK, CTRL Signals Daisy or T-Line Topology

The following tables provide a comprehensive routing guideline for each of the LPDDR5 signals based on memory down topology. For example, the trace impedance, the total trace length, the maximum length of the main trace routing can be derived by subtracting break-out and break-in trace segment length routed from total trace length. The signal trace width and minimum spacing and gaps (in mils) from edge to edge of signal traces are based on the default stackup.

The table below shows the stripline routing guidelinefor LPDDR5 memory down topology. The h value in the table represents the minimum substrate height from signal layer to reference layer.

Table 141.  Stripline Routing Guideline for LPDDR5 Memory Down Topology

The table below shows the microstrip routing for LPDDR5 memory down topology.

Table 142.  Microstrip Routing Guideline for LPDDR5 Memory Down Topology

Reset signal routing design also follows the CMD/ADD/CTRL routing design. Maintain at least 5x h of space between the Reset signal to other signals on the same layer (measured edge to edge). There is no requirement to have skew matching between the Reset and CLK signals.

Skew matching for LPDDR5 interfaces consists of both package routing skew and PCB physical routing skew. Skew matching of CA and CTRL with respect to the clock signals must be maintained to ensure signals at the receiver are correctly sampled. In addition, there are skew matching requirements for DQ and DQS within a byte group, DQS and CLK. The table below provides a detailed skew matching guideline to facilitate PCB trace routing efforts.

The length matching criteria in the table below represents a default PCB on an Intel platform board design. Skew matching criteria must be always followed in any other stackups.

Table 143.  Skew Matching Requirements for LPDDR5 Memory Down Topology

The LPDDR5 eye margin is sensitive to crosstalk, especially when signals are routed on deep layers in stackup; the deep-layer vertical transition induces greater vertical coupling between signals and hence more crosstalk.

The maximum data rate of LPDDR5 is highly dependent on the DDR memory down configuration and on the type of PCB. For example, with a Type-III PCB, the LPDDR5 interface can run at the maximum data rate for a single-rank x 32 bit LPDDR5 memory down configuration. A reduced data transfer rate is seen whenever 2 x rank LPDDR5 memory down configuration is used.

Table 144.  LPDDR5 Maximum Data Rate w.r.t Memory and PCB configuration
Memory LPDDR5
Signal group DQ
Board thickness (mil)

65mil or 120mil

(Routing must be on upper layers)

65mil or 120mil

(Routing must be on upper layers)
PCB trace impedance (ohm) Microstrip line: 45 Microstrip line: 45
Stripline: 40 Stripline: 40
Memory configuration Memory Down Memory Down
Number of rank 1 (x16 bits or x32 bits-Double Die) 2 (x 16 or x 32 bits)
Maximum data rate (MT/s) Refer to Agilex™ 5 data sheet Refer to Agilex™ 5 data sheet
Maximum length total (inch) Microstrip line: 3.0 Microstrip line: 3.0
Stripline: 4.0 Stripline: 4.0
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