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1. About the External Memory Interfaces Agilex™ 5 FPGA IP
2. Agilex™ 5 FPGA EMIF IP – Introduction
3. Agilex™ 5 FPGA EMIF IP – Product Architecture
4. Agilex™ 5 FPGA EMIF IP – End-User Signals
5. Agilex™ 5 FPGA EMIF IP – Simulating Memory IP
6. Intel® Agilex™ 5 FPGA EMIF IP - DDR4 Support
7. Intel® Agilex™ 5 FPGA EMIF IP - LPDDR4 Support
8. Intel® Agilex™ 5 FPGA EMIF IP - LPDDR5 Support
9. Agilex™ 5 FPGA EMIF IP – Timing Closure
10. Agilex™ 5 FPGA EMIF IP – Controller Optimization
11. Agilex™ 5 FPGA EMIF IP – Debugging
12. Document Revision History for External Memory Interfaces (EMIF) IP User Guide
3.2.1. Agilex™ 5 EMIF Architecture: I/O Subsystem
3.2.2. Agilex™ 5 EMIF Architecture: I/O SSM
3.2.3. Agilex™ 5 EMIF Architecture: HSIO Bank
3.2.4. Agilex™ 5 EMIF Architecture: I/O Lane
3.2.5. Agilex™ 5 EMIF Architecture: Input DQS Clock Tree
3.2.6. Agilex™ 5 EMIF Architecture: PHY Clock Tree
3.2.7. Agilex™ 5 EMIF Architecture: PLL Reference Clock Networks
3.2.8. Agilex™ 5 EMIF Architecture: Clock Phase Alignment
3.2.9. User Clock in Different Core Access Modes
6.4.3.1. 1 Rank x 8 Discrete (Memory Down) Topology
6.4.3.2. 1 Rank x 16 Discrete (Memory Down) Topology
6.4.3.3. VREF_CA/RESET Signal Routing Guidelines for 1 Rank x 8 and 1 Rank x 16 Discrete (Memory Down) Topology
6.4.3.4. Skew Matching Guidelines for DDR4 (Memory Down) Discrete Configurations
6.4.3.5. Power Delivery Recommendation for DDR4 Discrete Configurations
6.4.3.6. DDR4 Simulation Strategy
11.1. Interface Configuration Performance Issues
11.2. Functional Issue Evaluation
11.3. Timing Issue Characteristics
11.4. Verifying Memory IP Using the Signal Tap Logic Analyzer
11.5. Generating Traffic with the Test Engine IP
11.6. Guidelines for Developing HDL for Traffic Generator
11.7. Hardware Debugging Guidelines
11.8. Create a Simplified Design that Demonstrates the Same Issue
11.9. Measure Power Distribution Network
11.10. Measure Signal Integrity and Setup and Hold Margin
11.11. Vary Voltage
11.12. Operate at a Lower Speed
11.13. Determine Whether the Issue Exists in Previous Versions of Software
11.14. Determine Whether the Issue Exists in the Current Version of Software
11.15. Try A Different PCB
11.16. Try Other Configurations
11.17. Debugging Checklist
11.18. Categorizing Hardware Issues
11.19. Signal Integrity Issues
11.20. Characteristics of Signal Integrity Issues
11.21. Evaluating Signal Integrity Issues
11.22. Skew
11.23. Crosstalk
11.24. Power System
11.25. Clock Signals
11.26. Address and Command Signals
11.27. Read Data Valid Window and Eye Diagram
11.28. Write Data Valid Window and Eye Diagram
11.29. Hardware and Calibration Issues
11.30. Memory Timing Parameter Evaluation
11.31. Verify that the Board Has the Correct Memory Component or DIMM Installed
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11.6. Guidelines for Developing HDL for Traffic Generator
If you are not getting the expected response on the AXI bus when using your own traffic generator to test your EMIF IP on hardware, ensure that your traffic generator meets the following guidelines.
- The traffic generator issues transactions only after calibration has completed successfully. You can check the calibration status by using the AXI-Lite interface. In the EMIF example design, the cal_done_rst_n port on the ed_synth_axil_driver_0 corresponds to the calibration status. A value of cal_done_rst_n=1 indicates that the calibration has completed and passed.
Your traffic generator can begin to issue AXI-compliant transactions only after cal_done_rst_n=1.
Figure 70. cal_done_rst_n in ed_synth_axil_driver_0 - Ensure that all the AXI ports on the EMIF IP are driven by registers. To prevent registers from being merged and synthesized away, add the don't merge and preserve attributes to the registers driving the AXI port in your HDL.
Figure 71. Specifying dont_merge and preserve Attributes to all Registers Driving AXI Port