External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs

Download PDF
ID 817467
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the External Memory Interfaces Agilex™ 5 FPGA IP 2. Agilex™ 5 FPGA EMIF IP – Introduction 3. Agilex™ 5 FPGA EMIF IP – Product Architecture 4. Agilex™ 5 FPGA EMIF IP – End-User Signals 5. Agilex™ 5 FPGA EMIF IP – Simulating Memory IP 6. Intel® Agilex™ 5 FPGA EMIF IP - DDR4 Support 7. Intel® Agilex™ 5 FPGA EMIF IP - LPDDR4 Support 8. Intel® Agilex™ 5 FPGA EMIF IP - LPDDR5 Support 9. Agilex™ 5 FPGA EMIF IP – Timing Closure 10. Agilex™ 5 FPGA EMIF IP – Controller Optimization 11. Agilex™ 5 FPGA EMIF IP – Debugging 12. Document Revision History for External Memory Interfaces (EMIF) IP User Guide
1. About the External Memory Interfaces Agilex™ 5 FPGA IP x
1.1. Release Information
2. Agilex™ 5 FPGA EMIF IP – Introduction x
2.1. Agilex™ 5 EMIF IP Protocol and Feature Support 2.2. Agilex™ 5 EMIF IP Design Flow
2.2. Agilex™ 5 EMIF IP Design Flow x
2.2.1. Agilex™ 5 EMIF IP Design Checklist
3. Agilex™ 5 FPGA EMIF IP – Product Architecture x
3.1. Agilex™ 5 EMIF Architecture: Protocol and Maximum Interface Width Support 3.2. Agilex™ 5 EMIF Architecture: Introduction 3.3. Agilex™ 5 EMIF Sequencer 3.4. Agilex™ 5 EMIF Controller 3.5. Agilex™ 5 EMIF IP for Hard Processor Subsystem (HPS)
3.2. Agilex™ 5 EMIF Architecture: Introduction x
3.2.1. Agilex™ 5 EMIF Architecture: I/O Subsystem 3.2.2. Agilex™ 5 EMIF Architecture: I/O SSM 3.2.3. Agilex™ 5 EMIF Architecture: HSIO Bank 3.2.4. Agilex™ 5 EMIF Architecture: I/O Lane 3.2.5. Agilex™ 5 EMIF Architecture: Input DQS Clock Tree 3.2.6. Agilex™ 5 EMIF Architecture: PHY Clock Tree 3.2.7. Agilex™ 5 EMIF Architecture: PLL Reference Clock Networks 3.2.8. Agilex™ 5 EMIF Architecture: Clock Phase Alignment 3.2.9. User Clock in Different Core Access Modes
3.2.3. Agilex™ 5 EMIF Architecture: HSIO Bank x
3.2.3.1. Pin Placement 3.2.3.2. HSIO Sub-Bank Usage
3.3. Agilex™ 5 EMIF Sequencer x
3.3.1. Agilex™ 5 Mailbox Structure and Register Definitions
3.3.1. Agilex™ 5 Mailbox Structure and Register Definitions x
3.3.1.1. Mailbox Supported Commands 3.3.1.2. Mailbox Command Definitions
3.4. Agilex™ 5 EMIF Controller x
3.4.1. Hard Memory Controller
3.4.1. Hard Memory Controller x
3.4.1.1. Hard Memory Controller Features
4. Agilex™ 5 FPGA EMIF IP – End-User Signals x
4.1. Agilex™ 5 FPGA EMIF IP Interfaces for DDR4 4.2. Agilex™ 5 FPGA EMIF IP Interfaces for LPDDR4 4.3. Agilex™ 5 FPGA EMIF IP Interfaces for LPDDR5 4.4. Agilex™ 5 FPGA EMIF IP Interfaces for EMIF Calibration Component
4.1. Agilex™ 5 FPGA EMIF IP Interfaces for DDR4 x
4.1.1. ref_clk for EMIF 4.1.2. core_init_n for EMIF 4.1.3. usr_async_clk for EMIF 4.1.4. usr_clk for EMIF 4.1.5. usr_rst_n for EMIF 4.1.6. s0_axi4 for EMIF 4.1.7. mem for EMIF 4.1.8. oct for EMIF
4.2. Agilex™ 5 FPGA EMIF IP Interfaces for LPDDR4 x
4.2.1. ref_clk for EMIF 4.2.2. core_init_n for EMIF 4.2.3. usr_async_clk for EMIF 4.2.4. usr_clk for EMIF 4.2.5. usr_rst_n for EMIF 4.2.6. s0_axi4 for EMIF 4.2.7. mem for EMIF 4.2.8. oct for EMIF
4.3. Agilex™ 5 FPGA EMIF IP Interfaces for LPDDR5 x
4.3.1. ref_clk for EMIF 4.3.2. core_init_n for EMIF 4.3.3. usr_async_clk for EMIF 4.3.4. usr_clk for EMIF 4.3.5. usr_rst_n for EMIF 4.3.6. s0_axi4 for EMIF 4.3.7. oct for EMIF
4.4. Agilex™ 5 FPGA EMIF IP Interfaces for EMIF Calibration Component x
4.4.1. s0_axi4lite_clk for EMIF 4.4.2. s0_axi4lite_rst_n for EMIF 4.4.3. s0_axil for EMIF
5. Agilex™ 5 FPGA EMIF IP – Simulating Memory IP x
5.1. Simulation Walkthrough
5.1. Simulation Walkthrough x
5.1.1. Calibration 5.1.2. Simulation Scripts 5.1.3. Functional Simulation with Verilog HDL 5.1.4. Simulating the Design Example
6. Intel® Agilex™ 5 FPGA EMIF IP - DDR4 Support x
6.1. Intel® Agilex™ 5 FPGA EMIF IP Parameters for DDR4 6.2. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning 6.3. Agilex™ 5 EMIF Pin Swapping Guidelines 6.4. DDR4 Layout Design Guidelines
6.1. Intel® Agilex™ 5 FPGA EMIF IP Parameters for DDR4 x
6.1.1. Agilex™ 5 FPGA EMIF IP Parameter for DDR4 6.1.2. Intel Agilex 5 FPGA EMIF Memory Device Description IP (DDR4) Parameter Descriptions
6.2. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning x
6.2.1. Intel® Agilex™ 5 FPGA EMIF IP Resources 6.2.2. Pin Guidelines for Intel® Agilex™ 5 FPGA EMIF IP 6.2.3. Pin Placements for Intel® Agilex™ 5 FPGA DDR4 EMIF IP
6.2.1. Intel® Agilex™ 5 FPGA EMIF IP Resources x
6.2.1.1. OCT 6.2.1.2. PLL
6.2.2. Pin Guidelines for Intel® Agilex™ 5 FPGA EMIF IP x
6.2.2.1. Intel® Agilex™ 5 FPGA EMIF IP Pin and Resource Planning
6.2.2.1. Intel® Agilex™ 5 FPGA EMIF IP Pin and Resource Planning x
6.2.2.1.1. Intel® Agilex™ 5 FPGA EMIF IP Interface Pins 6.2.2.1.2. Estimating Pin Requirements 6.2.2.1.3. Maximum Number of Interfaces
6.2.3. Pin Placements for Intel® Agilex™ 5 FPGA DDR4 EMIF IP x
6.2.3.1. Address and Command Pin Placement for DDR4 6.2.3.2. DDR4 Data Width Mapping 6.2.3.3. General Guidelines 6.2.3.4. Specific Pin Connection Requirements 6.2.3.5. Command and Address Signals 6.2.3.6. Clock Signals 6.2.3.7. Data, Data Strobes, DM/DBI, and Optional ECC Signals
6.3. Agilex™ 5 EMIF Pin Swapping Guidelines x
6.3.1. DDR4 Byte Lane Swapping 6.3.2. DDR4 Address and Command and CLK Lane 6.3.3. DDR4 Interface x8 Data Lane 6.3.4. DDR4 Interface x4 Data Lane
6.4. DDR4 Layout Design Guidelines x
6.4.1. DDR4 PCB Stackup and Design Considerations 6.4.2. DDR4 General Design Considerations 6.4.3. DDR4 Routing Guidelines - Memory-Down (Discrete) Topologies
6.4.3. DDR4 Routing Guidelines - Memory-Down (Discrete) Topologies x
6.4.3.1. 1 Rank x 8 Discrete (Memory Down) Topology 6.4.3.2. 1 Rank x 16 Discrete (Memory Down) Topology 6.4.3.3. VREF_CA/RESET Signal Routing Guidelines for 1 Rank x 8 and 1 Rank x 16 Discrete (Memory Down) Topology 6.4.3.4. Skew Matching Guidelines for DDR4 (Memory Down) Discrete Configurations 6.4.3.5. Power Delivery Recommendation for DDR4 Discrete Configurations 6.4.3.6. DDR4 Simulation Strategy
7. Intel® Agilex™ 5 FPGA EMIF IP - LPDDR4 Support x
7.1. Intel® Agilex™ 5 FPGA EMIF IP Parameters for LPDDR4 7.2. Intel® Agilex™ 5 FPGA EMIF IP Pin and Resource Planning 7.3. LPDDR4 Layout Design Guidelines
7.1. Intel® Agilex™ 5 FPGA EMIF IP Parameters for LPDDR4 x
7.1.1. Agilex™ 5 FPGA EMIF IP Parameter for LPDDR4 7.1.2. Intel Agilex 5 FPGA EMIF Memory Device Description IP (LPDDR4) Parameter Descriptions
7.2. Intel® Agilex™ 5 FPGA EMIF IP Pin and Resource Planning x
7.2.1. Intel® Agilex™ 5 FPGA EMIF IP Interface Pins 7.2.2. Intel® Agilex™ 5 FPGA EMIF IP Resources 7.2.3. Pin Guidelines for Intel® Agilex™ 5 FPGA EMIF IP
7.2.1. Intel® Agilex™ 5 FPGA EMIF IP Interface Pins x
7.2.1.1. Estimating Pin Requirements 7.2.1.2. LPDDR4 Component Options 7.2.1.3. Maximum Number of Interfaces
7.2.2. Intel® Agilex™ 5 FPGA EMIF IP Resources x
7.2.2.1. OCT 7.2.2.2. PLL
7.2.3. Pin Guidelines for Intel® Agilex™ 5 FPGA EMIF IP x
7.2.3.1. General Guidelines 7.2.3.2. Specific Pin Connection Requirements 7.2.3.3. Command and Address Signals 7.2.3.4. Clock Signals 7.2.3.5. Address and Command Pin Placement for LPDDR4 7.2.3.6. Pin Placements for Agilex™ 5 FPGA EMIF IP for LPDDR4 7.2.3.7. Pin Swapping Guidelines
7.3. LPDDR4 Layout Design Guidelines x
7.3.1. LPDDR4 PCB Stackup and Design Considerations 7.3.2. LPDDR4 General Design Considerations 7.3.3. LPDDR4 Interface Design Guidelines
7.3.3. LPDDR4 Interface Design Guidelines x
7.3.3.1. LPDDR4 Discrete Component/Memory Down Topology (up to 32 bits interface) 7.3.3.2. LPDDR4 Simulation Strategy
8. Intel® Agilex™ 5 FPGA EMIF IP - LPDDR5 Support x
8.1. Intel Agilex 5 FPGA EMIF IP Parameters for LPDDR5 8.2. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning 8.3. LPDDR5 Layout Design Guidelines
8.1. Intel Agilex 5 FPGA EMIF IP Parameters for LPDDR5 x
8.1.1. Agilex™ 5 FPGA EMIF IP Parameter for LPDDR5 8.1.2. Intel Agilex 5 FPGA EMIF Memory Device Description IP (LPDDR5) Parameter Descriptions
8.2. Agilex™ 5 FPGA EMIF IP Pin and Resource Planning x
8.2.1. Agilex™ 5 FPGA EMIF IP Interface Pins 8.2.2. Agilex™ 5 FPGA EMIF IP Resources 8.2.3. Pin Guidelines for Agilex™ 5 FPGA EMIF IP 8.2.4. Pin Placements for Intel Agilex 5 FPGA LPDDR5 EMIF IP
8.2.1. Agilex™ 5 FPGA EMIF IP Interface Pins x
8.2.1.1. Estimating Pin Requirements 8.2.1.2. LPDDR5 Component Options 8.2.1.3. Maximum Number of Interfaces
8.2.2. Agilex™ 5 FPGA EMIF IP Resources x
8.2.2.1. OCT 8.2.2.2. PLL
8.2.3. Pin Guidelines for Agilex™ 5 FPGA EMIF IP x
8.2.3.1. General Guidelines - LPDDR5 8.2.3.2. Specific Pin Connection Requirements 8.2.3.3. Command and Address Signals 8.2.3.4. Clock Signals
8.2.4. Pin Placements for Intel Agilex 5 FPGA LPDDR5 EMIF IP x
8.2.4.1. Address and Command Pin Placement for LPDDR5 8.2.4.2. LPDDR5 Data Width Mapping 8.2.4.3. LPDDR5 Byte Lane Swapping
8.3. LPDDR5 Layout Design Guidelines x
8.3.1. LPDDR5 PCB Stackup and Design Considerations 8.3.2. LPDDR5 General Design Considerations 8.3.3. LPDDR5 Interface Design Guidelines
8.3.3. LPDDR5 Interface Design Guidelines x
8.3.3.1. LPDDR5 Discrete Component/Memory Down Topology (Single Rank or Dual-Rank) 8.3.3.2. Example of an LPDDR5 Layout on an Intel FPGA Platform Board 8.3.3.3. LPDDR5 Simulation Strategy
9. Agilex™ 5 FPGA EMIF IP – Timing Closure x
9.1. Timing Closure 9.2. Optimizing Timing
9.1. Timing Closure x
9.1.1. Timing Analysis
9.1.1. Timing Analysis x
9.1.1.1. PHY or Core
10. Agilex™ 5 FPGA EMIF IP – Controller Optimization x
10.1. Interface Standard 10.2. Bank Management Efficiency 10.3. Data Transfer 10.4. Improving Controller Efficiency
10.4. Improving Controller Efficiency x
10.4.1. Frequency of Operation 10.4.2. Series of Reads or Writes
11. Agilex™ 5 FPGA EMIF IP – Debugging x
11.1. Interface Configuration Performance Issues 11.2. Functional Issue Evaluation 11.3. Timing Issue Characteristics 11.4. Verifying Memory IP Using the Signal Tap Logic Analyzer 11.5. Generating Traffic with the Test Engine IP 11.6. Guidelines for Developing HDL for Traffic Generator 11.7. Hardware Debugging Guidelines 11.8. Create a Simplified Design that Demonstrates the Same Issue 11.9. Measure Power Distribution Network 11.10. Measure Signal Integrity and Setup and Hold Margin 11.11. Vary Voltage 11.12. Operate at a Lower Speed 11.13. Determine Whether the Issue Exists in Previous Versions of Software 11.14. Determine Whether the Issue Exists in the Current Version of Software 11.15. Try A Different PCB 11.16. Try Other Configurations 11.17. Debugging Checklist 11.18. Categorizing Hardware Issues 11.19. Signal Integrity Issues 11.20. Characteristics of Signal Integrity Issues 11.21. Evaluating Signal Integrity Issues 11.22. Skew 11.23. Crosstalk 11.24. Power System 11.25. Clock Signals 11.26. Address and Command Signals 11.27. Read Data Valid Window and Eye Diagram 11.28. Write Data Valid Window and Eye Diagram 11.29. Hardware and Calibration Issues 11.30. Memory Timing Parameter Evaluation 11.31. Verify that the Board Has the Correct Memory Component or DIMM Installed
11.1. Interface Configuration Performance Issues x
11.1.1. Interface Configuration Bottleneck and Efficiency Issues
11.2. Functional Issue Evaluation x
11.2.1. Intel® IP Memory Model 11.2.2. Vendor Memory Model 11.2.3. Transcript Window Messages
11.3. Timing Issue Characteristics x
11.3.1. Evaluating FPGA Timing Issues 11.3.2. Evaluating External Memory Interface Timing Issues
1. About the External Memory Interfaces Agilex™ 5 FPGA IP
2. Agilex™ 5 FPGA EMIF IP – Introduction
3. Agilex™ 5 FPGA EMIF IP – Product Architecture
4. Agilex™ 5 FPGA EMIF IP – End-User Signals
5. Agilex™ 5 FPGA EMIF IP – Simulating Memory IP
6. Intel® Agilex™ 5 FPGA EMIF IP - DDR4 Support
7. Intel® Agilex™ 5 FPGA EMIF IP - LPDDR4 Support
8. Intel® Agilex™ 5 FPGA EMIF IP - LPDDR5 Support
9. Agilex™ 5 FPGA EMIF IP – Timing Closure
10. Agilex™ 5 FPGA EMIF IP – Controller Optimization
11. Agilex™ 5 FPGA EMIF IP – Debugging
12. Document Revision History for External Memory Interfaces (EMIF) IP User Guide

7.1.2. Intel Agilex 5 FPGA EMIF Memory Device Description IP (LPDDR4) Parameter Descriptions

The following topics describe the parameters available on each tab of the IP parameter editor, which you can use to configure your IP. Each parameter with an adjacent checkbox can be auto-computed. The checkbox to the left of the parameter controls whether its value is auto-computed (true) or set manually (false). If there is no checkbox to the left of a parameter, then it must be set manually.
Table 99.  Group: Configuration Save
Display Name Description
Configuration Filepath

Filepath to Save to (.qprs extension)

(Identifier: MEM_CONFIG_FILE_QPRS)
Table 100.  Group: High-Level Parameters
Display Name Description
Memory Format

Specifies the packaging format of the memory device

(Identifier: MEM_FORMAT)
Number of Channels in Memory Package

Number of Channels in Memory Package. This value must be consistent with the same MEM_NUM_CHANNELS parameter in the top-level EMIF IP GUI.

(Identifier: LPDDR4_MEM_DEVICE_NUM_CHANNELS)
Number of Ranks Per Channel

Number of Ranks Per Channel in Memory Package. This value must be consistent with the same MEM_NUM_RANKS parameter in the top-level EMIF IP GUI.

(Identifier: LPDDR4_MEM_DEVICE_NUM_RANKS_PER_CHANNEL)
Number of Individual DRAM Components Per Rank

Number of Individual DRAM Components Per Rank in Memory Package. This value must be consistent with the same MEM_COMPS_PER_RANK parameter in the top-level EMIF IP GUI.

(Identifier: LPDDR4_MEM_DEVICE_NUM_COMPS_PER_RANK)
Density of Each Memory Die per Channel

Specifies the density of each channel in the memory die in Gb

(Identifier: LPDDR4_MEM_DEVICE_DENSITY_GBITS)
Enable Write Data Bus Inversion

Enables Write Data Bus Inversion

(Identifier: LPDDR4_MEM_DEVICE_WR_DBI_EN)
Enable Data Mask

Enables Data Masking for write operations

(Identifier: LPDDR4_MEM_DEVICE_DM_EN)
Table 101.  Group: Memory Interface Parameters / Data Bus
Display Name Description
DQ Width per DRAM Component

Specifies the DQ width of each LPDDR4 DRAM component. As byte mode is not supported, this value is always 16. To form x32 LP4 interfaces, select 2 components per rank at the EMIF IP level.

(Identifier: LPDDR4_MEM_DEVICE_DQ_WIDTH)
Total DQ Width Per Channel

Total DQ Width Per Channel. For LPDDR4 packages, this is the product of the per-DRAM DQ Width and Number of Individual DRAM Components per Rank.

(Identifier: LPDDR4_MEM_DEVICE_TOTAL_DQ_WIDTH_PER_CHANNEL)
Burst Length

Burst Length

(Identifier: LPDDR4_MEM_DEVICE_BURST_LENGTH)
Table 102.  Group: Memory Interface Parameters / Device Topology
Display Name Description
Device Row Address Width

Specifies the row address width of this LPDDR4 DRAM component. This value is auto-derived from the specified component density.

(Identifier: LPDDR4_MEM_DEVICE_ROW_ADDR_WIDTH)
Device Bank Address Width

Specifies the bank address width. This value is fixed as per the JEDEC standard and cannot be changed.

(Identifier: LPDDR4_MEM_DEVICE_BANK_ADDR_WIDTH)
Device Column Address Width

Specifies the column address width of this LPDDR4 DRAM component. This value is fixed for all component densities as per the JEDEC standard and cannot be changed.

(Identifier: LPDDR4_MEM_DEVICE_COL_ADDR_WIDTH)
Table 103.  Group: Memory Timing Parameters / Timing Parameters
Display Name Description
Memory Clock Frequency

Specifies the Write Clock Frequency

Note: This parameter can be auto-computed.

(Identifier: PHY_MEMCLK_FREQ_MHZ)
Memory Speedbin

Maximum Data Rate for which this memory device is rated for

(Identifier: LPDDR4_MEM_DEVICE_SPEEDBIN)
Memory Write Latency Set

Selects the Write Latency Set for this device. Selection affects auto-calculation of Write Latency.

(Identifier: LPDDR4_MEM_DEVICE_WLS)
Memory Read Latency

Read Latency of the memory device in clock cycles

Note: This parameter can be auto-computed.

(Identifier: LPDDR4_MEM_DEVICE_CL_CYC)
Memory Write Latency

Write Latency in clock cycles

Note: This parameter can be auto-computed.

(Identifier: LPDDR4_MEM_DEVICE_CWL_CYC)
Table 104.  Group: Memory Timing Parameters / Pre- and Post-Amble Options
Display Name Description
Read Preamble Cycles

Duration of read preamble in cycles

(Identifier: LPDDR4_MEM_DEVICE_RD_PREAMBLE_CYC)
Read Postamble Cycles

Duration of read postamble in cycles

(Identifier: LPDDR4_MEM_DEVICE_RD_POSTAMBLE_CYC)
Write Postamble Cycles

Duration of write postamble in cycles

(Identifier: LPDDR4_MEM_DEVICE_WR_POSTAMBLE_CYC)
Table 105.  Group: Memory Timing Parameters / Advanced Timing Parameters
Display Name Description
tSR

Minimum duration (Entry to Exit) of Self Refresh in nanoseconds

Note: This parameter can be auto-computed.

(Identifier: LPDDR4_MEM_DEVICE_TSR_NS)
tXSR

Self-Refresh Exit to Next Valid Command Delay Time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR4_MEM_DEVICE_TXSR_NS)
tXP

Exit Power-Down to Next Valid Command Delay Time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR4_MEM_DEVICE_TXP_NS)
tCCD

CAS-to-CAS Delay in memory clock cycles

Note: This parameter can be auto-computed.

(Identifier: LPDDR4_MEM_DEVICE_TCCD_CYC)
tRTP

Internal READ to PRECHARGE Command Delay Time in nanoseconds

Note: This parameter can be auto-computed.

(Identifier: LPDDR4_MEM_DEVICE_TRTP_NS)
tRCD

RAS-to-CAS Delay in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR4_MEM_DEVICE_TRCD_NS)
tRPpb

Per-Bank Precharge Time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR4_MEM_DEVICE_TRPPB_NS)
tRPab

All-Bank Precharge Time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR4_MEM_DEVICE_TRPAB_NS)
tRAS

Row Active Time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR4_MEM_DEVICE_TRAS_NS)
tWR

Write Recovery Time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR4_MEM_DEVICE_TWR_NS)
tWTR

Write-to-Read Delay in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR4_MEM_DEVICE_TWTR_NS)
tRRD

RAS-to-RAS (Active Bank-A to Active Bank-B) Delay Time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR4_MEM_DEVICE_TRRD_NS)
tPPD

Precharge-to-precharge delay in memory clock cycles

Note: This parameter can be auto-computed.

(Identifier: LPDDR4_MEM_DEVICE_TPPD_CYC)
tFAW

Four-bank ACTIVE window time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR4_MEM_DEVICE_TFAW_NS)
tRC

Activate-to-Activate command period (same bank) in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR4_MEM_DEVICE_TRC_NS)
tREFW

Refresh window time in milliseconds

Note: This parameter can be auto-computed.

(Identifier: LPDDR4_MEM_DEVICE_TREFW_MS)
Min Number of Refs Reqd

Minimum Number of Refreshes Required

Note: This parameter can be auto-computed.

(Identifier: LPDDR4_MEM_DEVICE_MINNUMREFSREQ)
tREFI

Refresh Interval Time in us

Note: This parameter can be auto-computed.

(Identifier: LPDDR4_MEM_DEVICE_TREFI_NS)
tRFCab

All-Bank Refresh Cycle Time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR4_MEM_DEVICE_TRFCAB_NS)
tRFCpb

Per-Bank Refresh Cycle Time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR4_MEM_DEVICE_TRFCPB_NS)
tCKE

CKE Minimum Pulse Width time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR4_MEM_DEVICE_TCKE_NS)
tCMDCKE

Delay from valid command to power-down-entry (CKE low) in nanoseconds

Note: This parameter can be auto-computed.

(Identifier: LPDDR4_MEM_DEVICE_TCMDCKE_NS)
tCKELCK

Valid clock requirement after power-down-entry in nanoseconds

Note: This parameter can be auto-computed.

(Identifier: LPDDR4_MEM_DEVICE_TCKELCK_NS)
tCSCKE

Valid CS requirement before power-down-entry (CKE low) in nanoseconds

Note: This parameter can be auto-computed.

(Identifier: LPDDR4_MEM_DEVICE_TCSCKE_NS)
tCKCKEH

Valid clock requirement before power-down-exit in nanoseconds

Note: This parameter can be auto-computed.

(Identifier: LPDDR4_MEM_DEVICE_TCKCKEH_NS)
tCSCKEH

Valid CS requirement before power-down-exit (CKE high) in nanoseconds

Note: This parameter can be auto-computed.

(Identifier: LPDDR4_MEM_DEVICE_TCSCKEH_NS)
tMRWCKEL

Delay from MRW command to power-down-entry (CKE low) in nanoseconds

Note: This parameter can be auto-computed.

(Identifier: LPDDR4_MEM_DEVICE_TMRWCKEL_NS)
tZQCKE

Delay from ZQCal Start command to power-down-entry (CKE low) in nanoseconds

Note: This parameter can be auto-computed.

(Identifier: LPDDR4_MEM_DEVICE_TZQCKE_NS)
tMRR

Mode Register Read Command Period Time in memory clock cycles

Note: This parameter can be auto-computed.

(Identifier: LPDDR4_MEM_DEVICE_TMRR_CYC)
tMRW

Mode Register Write Command Period Time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR4_MEM_DEVICE_TMRW_NS)
tMRD

Mode Register Set Command Period Time in ns

Note: This parameter can be auto-computed.

(Identifier: LPDDR4_MEM_DEVICE_TMRD_NS)
tESCKE

Delay from SRE command to CKE Input low

Note: This parameter can be auto-computed.

(Identifier: LPDDR4_MEM_DEVICE_TESCKE_NS)
tZQCAL

ZQ calibration time in microseconds

Note: This parameter can be auto-computed.

(Identifier: LPDDR4_MEM_DEVICE_TZQCAL_US)
tZQLAT

ZQcal Latch time in nanoseconds

Note: This parameter can be auto-computed.

(Identifier: LPDDR4_MEM_DEVICE_TZQLAT_NS)
tDQSCK_MAX

Maximum DQS output access time from CK in nanoseconds

Note: This parameter can be auto-computed.

(Identifier: LPDDR4_MEM_DEVICE_TDQSCK_MAX_PS)
tDQSCK_MIN

Minimum DQS output access time from CK in nanoseconds

Note: This parameter can be auto-computed.

(Identifier: LPDDR4_MEM_DEVICE_TDQSCK_MIN_PS)
tCKCKEL

Clock valid requirements after power-down-entry (CKE low) in nanoseconds

Note: This parameter can be auto-computed.

(Identifier: LPDDR4_MEM_DEVICE_TCKCKEL_NS)
tCKELCMD

Valid command requirement after CKE input low in nanoseconds

Note: This parameter can be auto-computed.

(Identifier: LPDDR4_MEM_DEVICE_TCKELCMD_NS)
tCKEHCMD

Valid command requirement after CKE input high in nanoseconds

Note: This parameter can be auto-computed.

(Identifier: LPDDR4_MEM_DEVICE_TCKEHCMD_NS)
Level Two Title