Intel® Simics® Simulator for Intel® FPGAs: Agilex™ 5 E-Series Virtual Platform User Guide

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ID 786901
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. About This Document 2. Agilex™ 5 E-Series Intel® Simics® Virtual Platforms 3. Agilex™ 5 E-Series Virtual Platform Component Intel® Simics® Models 4. Running a Simulation with the Agilex™ 5 E-Series HPS Model 5. Supported Use Cases 6. Troubleshooting Issues When Migrating Software from Intel® Simics® to Hardware A. Document Revision History
1. About This Document x
1.1. Terminology 1.2. List of Acronyms
2. Agilex™ 5 E-Series Intel® Simics® Virtual Platforms x
2.1. Agilex™ 5 E-Series Universal Virtual Platform
2.1. Agilex™ 5 E-Series Universal Virtual Platform x
2.1.1. Agilex™ 5 E-Series Universal Virtual Platform Overview 2.1.2. Agilex™ 5 E-Series Universal Virtual Platform User-Configurable Parameters 2.1.3. Agilex™ 5 E-Series Virtual Platform Key Capabilities
2.1.1. Agilex™ 5 E-Series Universal Virtual Platform Overview x
2.1.1.1. Agilex™ 5 HPS Component 2.1.1.2. HPS Subsystem Component 2.1.1.3. FPGA Fabric Design 2.1.1.4. qsys_top Component 2.1.1.5. FPGA Component 2.1.1.6. Board Component 2.1.1.7. System Component 2.1.1.8. Target Script
2.1.3. Agilex™ 5 E-Series Virtual Platform Key Capabilities x
2.1.3.1. Boot-To-Operating System Prompt 2.1.3.2. Basic Ethernet 2.1.3.3. CPU Power-On and Boot Core Selection 2.1.3.4. Reset Flow 2.1.3.5. General Purpose I/O (GPIO) Loopback 2.1.3.6. USB Disks Hot-Plug Support 2.1.3.7. On-Chip Memory IP FPGA Fabric Example Design 2.1.3.8. FPGA-to-HPS Bridges 2.1.3.9. Exercising Peripheral Subsystem in FPGA Fabric Design 2.1.3.10. USB Controller Host/Device Mode Configuration 2.1.3.11. B0 Silicon Features Selection
3. Agilex™ 5 E-Series Virtual Platform Component Intel® Simics® Models x
3.1. Agilex™ 5 E-Series HPS Intel® Simics® Model 3.2. Virtual Platform HPS Subsystem Components 3.3. Virtual Platform qsys_top Components 3.4. Virtual Platform Board Components 3.5. Modeling Support Limitations
3.1. Agilex™ 5 E-Series HPS Intel® Simics® Model x
3.1.1. Agilex™ 5 E-Series HPS Intel® Simics® Model Architecture 3.1.2. PSS Subsystem Components 3.1.3. MPU and APS Subsystem 3.1.4. MPFE Subsystem 3.1.5. Additional Agilex™ 5 E-Series HPS Components 3.1.6. Agilex™ 5 E-Series B0 Features Support
3.2. Virtual Platform HPS Subsystem Components x
3.2.1. External Memory Interface (EMIF) 3.2.2. Security Device Manager (SDM)
3.3. Virtual Platform qsys_top Components x
3.3.1. FPGA Fabric
3.4. Virtual Platform Board Components x
3.4.1. Marvel EMAC PHY 3.4.2. SD Card Device 3.4.3. ONFI NAND Memory Device 3.4.4. SPI Flash Device 3.4.5. AT24Cxx EEPROM Device 3.4.6. I3C Device 3.4.7. USB Disk Device 3.4.8. Intel® Simics® Text Console
4. Running a Simulation with the Agilex™ 5 E-Series HPS Model x
4.1. Prerequisites 4.2. Intel® Simics® Simulation Setup for the Agilex™ 5 E-Series Device 4.3. Starting the Simulation 4.4. Getting Device Information from the Intel® Simics® Model
1. About This Document
2. Agilex™ 5 E-Series Intel® Simics® Virtual Platforms
3. Agilex™ 5 E-Series Virtual Platform Component Intel® Simics® Models
4. Running a Simulation with the Agilex™ 5 E-Series HPS Model
5. Supported Use Cases
6. Troubleshooting Issues When Migrating Software from Intel® Simics® to Hardware
A. Document Revision History

2. Agilex™ 5 E-Series Intel® Simics® Virtual Platforms

The Intel® Simics® model of the Agilex™ 5 E-Series FPGA SoC hard processor system (HPS) implements the simulated functionality of the HPS. This model is instantiated as part of a virtual platform along with other components.

The embedded software runs in the simulated processors of Agilex™ 5 E-Series HPS device Intel® Simics® model interacting with the simulation of other internal and external device components. The virtual platforms combine the HPS Intel® Simics® model with other component models to provide a full system simulation.

For more information about the difference between a virtual platform and a model in Intel® Simics® simulation, refer to Device Model and Virtual Platforms in the Intel® Simics® Simulator for Intel® FPGAs User Guide.

The Agilex™ 5 E-Series Intel® Simics® virtual platform follows the Intel® Simics® Simulator for Intel® FPGAs virtual platform philosophy in which it attempts to match the architecture defined in the Quartus® Prime GHRD for this device to be used in real hardware. The Golden Hardware Reference Design (GHRD), part of the Golden System Reference Design (GSRD), is an Quartus® Prime project that contains a full HPS design for the Agilex™ 5 E-Series SoC Development Kit. The GHRD has connections to a boot source, SDRAM memory, and other peripherals on the development board. The purpose of the hardware design is to configure the SoC, including the FPGA portion, the HPS pin multiplexers and I/Os, and the DDRAM. All software projects depend on a hardware design.

The Intel Agilex 5 E-Series universal virtual platform provides a virtual GHRD that allows exercising the HPS software in an Intel® Simics® simulation. For this purpose, the virtual platform consists of the following key components:

Table 3.   Agilex™ 5 E-Series Intel® Simics® Virtual Platform Components
Component Description
HPS An Agilex™ 5 E-Series SoC FPGA HPS model (the HPS IP), including all the subsystems that integrates this.
HPS Subsystem Corresponds to the subsystem model that includes the HPS IP model of the Agilex™ 5 E-Series device and some of the top-level components that interact with it, such as the SDM and memory controller (EMIF).
FPGA Fabric Design Corresponds to the logic model that is implemented in the FPGA fabric. This is not implemented as a single component instead, each one of the modules included in this model is instantiated individually.
qsys_top Corresponds to the hardware design view that is being modeled, and corresponds to the qsys_top component seen from the Platform Designer under the GHRD (soc_inst instance). Under qsys_top, components such as the HPS subsystem and the FPGA Fabric design are instantiated.
FPGA A model that represents the top-level view of the hardware design from the FPGA device perspective corresponding to the GHRD in the Quartus® Prime project for the Agilex™ 5 E-Series device. This model instantiates qsys_top component.
Board A board model containing an Agilex™ 5 E-Series SoC FPGA device. This model integrates the FPGA model with board components such as flash devices (SD Card, QSPI, NAND), USB disks, Ethernet PHY, and connectors.
System A model that represents the complete system. It instantiates the board component and any other component not included as part of the board component.
Target Script The target script instantiates the system component in an Intel® Simics® simulation environment. This script defines any user-configurable parameters, the network configuration, and any run-time commands to use during the simulation.

For more information about the virtual platform structure defined for Intel® FPGA devices, refer to Understanding Target Scripts in the Intel® Simics® Simulator for Intel® FPGAs User Guide.

The Agilex™ 5 E-Series Virtual Platforms support Intel® Simics® simulations with the Agilex™ 5 E-Series HPS device model. The following sections describe the supported virtual platforms in detail.


Section Content
Agilex 5 E-Series Universal Virtual Platform

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