Intel® Simics® Simulator for Intel® FPGAs: Agilex™ 5 E-Series Virtual Platform User Guide

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ID 786901
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. About This Document 2. Agilex™ 5 E-Series Intel® Simics® Virtual Platforms 3. Agilex™ 5 E-Series Virtual Platform Component Intel® Simics® Models 4. Running a Simulation with the Agilex™ 5 E-Series HPS Model 5. Supported Use Cases 6. Troubleshooting Issues When Migrating Software from Intel® Simics® to Hardware A. Document Revision History
1. About This Document x
1.1. Terminology 1.2. List of Acronyms
2. Agilex™ 5 E-Series Intel® Simics® Virtual Platforms x
2.1. Agilex™ 5 E-Series Universal Virtual Platform
2.1. Agilex™ 5 E-Series Universal Virtual Platform x
2.1.1. Agilex™ 5 E-Series Universal Virtual Platform Overview 2.1.2. Agilex™ 5 E-Series Universal Virtual Platform User-Configurable Parameters 2.1.3. Agilex™ 5 E-Series Virtual Platform Key Capabilities
2.1.1. Agilex™ 5 E-Series Universal Virtual Platform Overview x
2.1.1.1. Agilex™ 5 HPS Component 2.1.1.2. HPS Subsystem Component 2.1.1.3. FPGA Fabric Design 2.1.1.4. qsys_top Component 2.1.1.5. FPGA Component 2.1.1.6. Board Component 2.1.1.7. System Component 2.1.1.8. Target Script
2.1.3. Agilex™ 5 E-Series Virtual Platform Key Capabilities x
2.1.3.1. Boot-To-Operating System Prompt 2.1.3.2. Basic Ethernet 2.1.3.3. CPU Power-On and Boot Core Selection 2.1.3.4. Reset Flow 2.1.3.5. General Purpose I/O (GPIO) Loopback 2.1.3.6. USB Disks Hot-Plug Support 2.1.3.7. On-Chip Memory IP FPGA Fabric Example Design 2.1.3.8. FPGA-to-HPS Bridges 2.1.3.9. Exercising Peripheral Subsystem in FPGA Fabric Design 2.1.3.10. USB Controller Host/Device Mode Configuration 2.1.3.11. B0 Silicon Features Selection
3. Agilex™ 5 E-Series Virtual Platform Component Intel® Simics® Models x
3.1. Agilex™ 5 E-Series HPS Intel® Simics® Model 3.2. Virtual Platform HPS Subsystem Components 3.3. Virtual Platform qsys_top Components 3.4. Virtual Platform Board Components 3.5. Modeling Support Limitations
3.1. Agilex™ 5 E-Series HPS Intel® Simics® Model x
3.1.1. Agilex™ 5 E-Series HPS Intel® Simics® Model Architecture 3.1.2. PSS Subsystem Components 3.1.3. MPU and APS Subsystem 3.1.4. MPFE Subsystem 3.1.5. Additional Agilex™ 5 E-Series HPS Components 3.1.6. Agilex™ 5 E-Series B0 Features Support
3.2. Virtual Platform HPS Subsystem Components x
3.2.1. External Memory Interface (EMIF) 3.2.2. Security Device Manager (SDM)
3.3. Virtual Platform qsys_top Components x
3.3.1. FPGA Fabric
3.4. Virtual Platform Board Components x
3.4.1. Marvel EMAC PHY 3.4.2. SD Card Device 3.4.3. ONFI NAND Memory Device Limitations 3.4.4. SPI Flash Device 3.4.5. AT24Cxx EEPROM Device 3.4.6. I3C Device 3.4.7. USB Disk Device 3.4.8. Intel® Simics® Text Console
4. Running a Simulation with the Agilex™ 5 E-Series HPS Model x
4.1. Prerequisites 4.2. Intel® Simics® Simulation Setup for the Agilex™ 5 E-Series Device 4.3. Starting the Simulation 4.4. Getting Device Information from the Intel® Simics® Model
1. About This Document
2. Agilex™ 5 E-Series Intel® Simics® Virtual Platforms
3. Agilex™ 5 E-Series Virtual Platform Component Intel® Simics® Models
4. Running a Simulation with the Agilex™ 5 E-Series HPS Model
5. Supported Use Cases
6. Troubleshooting Issues When Migrating Software from Intel® Simics® to Hardware
A. Document Revision History

3.4.3. ONFI NAND Memory Device

The NAND Flash device connects to the Combo PHY through a NAND flash interface.

The NAND device supported corresponds to a generic ONFI NAND Flash device model compatible with ONFI 1.0 specification. The following table lists the limitations of the NAND Flash device together with the NAND Controller.

The parameters of the NAND device supported are as follows:

  • Data bytes per page: 512, 2048, 4096, 8192, or 16384.
  • Number of pages per block: 16 or 32 for devices with 512-byte pages, 64 for devices with 2048 or 4096-byte pages, 128 for devices with 8192-byte pages, and 1024 for devices with 16384-byte pages.
  • Bus width: Configurable 8 or 16 bits.
  • Spare area page size: Valid from 1 to 2208.
  • Blocks per LUN is configurable.

Ensure that the configuration values for page size and the spare area size are consistent with the values supported on the ONFI specification.

Limitations

The following table lists supported and unsupported features and commands:

Table 23.  Supported and Unsupported Features and Commands

Supported

Commands: Read ID, Read Parameter Page, Reset, Read Page, Block Erase, Program Page, Read Status, Read Status Enhanced, Change Read Column Address, Change Write Column Address.

Unsupported

ECC/EDC calculation.

One-time programmable (OTP) area entry.

Commands: Multiplane commands, Cache Operations commands, Copy Back Read, Copy Back Program, READ ID2.

Component: nand_flash

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