Intel® Simics® Simulator for Intel® FPGAs: Agilex™ 5 E-Series Virtual Platform User Guide

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ID 786901
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. About This Document 2. Agilex™ 5 E-Series Intel® Simics® Virtual Platforms 3. Agilex™ 5 E-Series Virtual Platform Component Intel® Simics® Models 4. Running a Simulation with the Agilex™ 5 E-Series HPS Model 5. Supported Use Cases 6. Troubleshooting Issues When Migrating Software from Intel® Simics® to Hardware A. Document Revision History
1. About This Document x
1.1. Terminology 1.2. List of Acronyms
2. Agilex™ 5 E-Series Intel® Simics® Virtual Platforms x
2.1. Agilex™ 5 E-Series Universal Virtual Platform
2.1. Agilex™ 5 E-Series Universal Virtual Platform x
2.1.1. Agilex™ 5 E-Series Universal Virtual Platform Overview 2.1.2. Agilex™ 5 E-Series Universal Virtual Platform User-Configurable Parameters 2.1.3. Agilex™ 5 E-Series Virtual Platform Key Capabilities
2.1.1. Agilex™ 5 E-Series Universal Virtual Platform Overview x
2.1.1.1. Agilex™ 5 HPS Component 2.1.1.2. HPS Subsystem Component 2.1.1.3. FPGA Fabric Design 2.1.1.4. qsys_top Component 2.1.1.5. FPGA Component 2.1.1.6. Board Component 2.1.1.7. System Component 2.1.1.8. Target Script
2.1.3. Agilex™ 5 E-Series Virtual Platform Key Capabilities x
2.1.3.1. Boot-To-Operating System Prompt 2.1.3.2. Basic Ethernet 2.1.3.3. CPU Power-On and Boot Core Selection 2.1.3.4. Reset Flow Target Script Simulating a Warm and Cold Reset 2.1.3.5. General Purpose I/O (GPIO) Loopback 2.1.3.6. USB Disks Hot-Plug Support 2.1.3.7. On-Chip Memory IP FPGA Fabric Example Design 2.1.3.8. FPGA-to-HPS Bridges 2.1.3.9. Exercising Peripheral Subsystem in FPGA Fabric Design 2.1.3.10. USB Controller Host/Device Mode Configuration 2.1.3.11. B0 Silicon Features Selection
3. Agilex™ 5 E-Series Virtual Platform Component Intel® Simics® Models x
3.1. Agilex™ 5 E-Series HPS Intel® Simics® Model 3.2. Virtual Platform HPS Subsystem Components 3.3. Virtual Platform qsys_top Components 3.4. Virtual Platform Board Components 3.5. Modeling Support Limitations
3.1. Agilex™ 5 E-Series HPS Intel® Simics® Model x
3.1.1. Agilex™ 5 E-Series HPS Intel® Simics® Model Architecture 3.1.2. PSS Subsystem Components 3.1.3. MPU and APS Subsystem 3.1.4. MPFE Subsystem 3.1.5. Additional Agilex™ 5 E-Series HPS Components 3.1.6. Agilex™ 5 E-Series B0 Features Support
3.2. Virtual Platform HPS Subsystem Components x
3.2.1. External Memory Interface (EMIF) 3.2.2. Security Device Manager (SDM)
3.3. Virtual Platform qsys_top Components x
3.3.1. FPGA Fabric
3.4. Virtual Platform Board Components x
3.4.1. Marvel EMAC PHY 3.4.2. SD Card Device 3.4.3. ONFI NAND Memory Device 3.4.4. SPI Flash Device 3.4.5. AT24Cxx EEPROM Device 3.4.6. I3C Device 3.4.7. USB Disk Device 3.4.8. Intel® Simics® Text Console
4. Running a Simulation with the Agilex™ 5 E-Series HPS Model x
4.1. Prerequisites 4.2. Intel® Simics® Simulation Setup for the Agilex™ 5 E-Series Device 4.3. Starting the Simulation 4.4. Getting Device Information from the Intel® Simics® Model
1. About This Document
2. Agilex™ 5 E-Series Intel® Simics® Virtual Platforms
3. Agilex™ 5 E-Series Virtual Platform Component Intel® Simics® Models
4. Running a Simulation with the Agilex™ 5 E-Series HPS Model
5. Supported Use Cases
6. Troubleshooting Issues When Migrating Software from Intel® Simics® to Hardware
A. Document Revision History

2.1.3.4. Reset Flow

The Agilex™ 5 E-Series Virtual Platform supports all key reset flows described in the Agilex™ 5 E-Series HPS Technical Reference Manual. Reset flows initiated by the CPU are simulated through the same mechanism in which the CPU writes to the appropriate addresses (that is, reset manager device).

Resets triggered by external hardware signaling are simulated using Intel® Simics® commands.

The following table describes the supported reset types and how to exercise them from a simulation:

Table 8.  Supported Reset Types
Reset Type Exercise Method Description

Power-on Reset

Not Supported.

The power-on reset is not supported because its effect is equivalent to restarting the simulation in a virtual platform simulation.

However, if this is required for some exceptional use cases, you can trigger the cold reset instead, as this resets most of the domains.

HPS Cold Reset

 system.board.hps-cold-reset

Simulates toggling the pin using the command registered in the board component.

HPS Warm Reset

 system.board.fpga.soc_inst.hps_subsys.agilex_hps.hps-warm-reset

Simulates a warm reset of the HPS without needing to trigger any other event.

This type of reset is not enabled through external means in hardware. The command is registered in the HPS component.

Watchdog reset

Software based

The watchdog timer peripheral in the HPS can be configured and enabled through software.

When the watchdog expires, the HPS is reset. A warm reset is supported after the watchdog timer expires.

Target Script Simulating a Warm and Cold Reset

The following example captures a target script issuing warm and cold reset in a simulation where the U-Boot SPL to U-Boot SSBL boot flow is being exercised. The example uses a script branch to set few breakpoints on messages displayed in the serial console. Initially, it waits for a message that U-Boot SSBL prints and then, the script issues a warm reset. At this time, the HPS is reset, and U-Boot SPL restarts printing the detected type of reset, which at this time is a warm reset. After the warm reset, the script waits again for U-Boot SSBL to print the same message and issues a cold reset. The U-Boot SPL is executed again, indicating that the reset type is a cold reset. 

$sd_image_filename = "sdcard.img"
$fsbl_image_filename = "u-boot-spl-dtb.bin"
$hps_cpu_freq_mhz = 800
$create_hps_sd_card = TRUE 
run-command-file "targets/agilex5e-universal/agilex5e-universal.simics"

script-branch{
    # Wait for U-Boot SSBL
	bp.console_string.wait-for system.board.fpga.soc_inst.hps_subsys.agilex_hps.console0.con "CPU:   Intel FPGA SoCFPGA Platform"
	echo "Breakpoint hit..."
	# Generate a Warm Reset
	system.board.fpga.soc_inst.hps_subsys.agilex_hps.hps-warm-reset
	bp.console_string.wait-for system.board.fpga.soc_inst.hps_subsys.agilex_hps.console0.con "Reset state: Warm [from SDM]"
	echo "Warm reset detected by U-Boot SPL"

	# Wait for U-Boot SSBL	
	bp.console_string.wait-for system.board.fpga.soc_inst.hps_subsys.agilex_hps.console0.con "CPU:   Intel FPGA SoCFPGA Platform"
	echo "Breakpoint hit..."
	# Generate a Cold Reset
	system.board.hps-cold-reset
	bp.console_string.wait-for system.board.fpga.soc_inst.hps_subsys.agilex_hps.console0.con "Reset state: "
	echo "Cold reset detected by U-Boot SPL"
}

The following output is observed in the Intel® Simics® CLI after executing the above target script: 

Connections:
       hps2fpga_0_down : system.board.fpga.soc_inst.example_design:design_mem_conn
              hps_conn : system.board.fpga.soc_inst.hps_subsys.emif:emif_conn

:
Breakpoint hit...
Warm reset detected by U-Boot SPL
Breakpoint hit...
Cold reset detected by U-Boot SPL
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