Intel® Simics® Simulator for Intel® FPGAs: Agilex™ 5 E-Series Virtual Platform User Guide

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ID 786901
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. About This Document 2. Agilex™ 5 E-Series Intel® Simics® Virtual Platforms 3. Agilex™ 5 E-Series Virtual Platform Component Intel® Simics® Models 4. Running a Simulation with the Agilex™ 5 E-Series HPS Model 5. Supported Use Cases 6. Troubleshooting Issues When Migrating Software from Intel® Simics® to Hardware A. Document Revision History
1. About This Document x
1.1. Terminology 1.2. List of Acronyms
2. Agilex™ 5 E-Series Intel® Simics® Virtual Platforms x
2.1. Agilex™ 5 E-Series Universal Virtual Platform
2.1. Agilex™ 5 E-Series Universal Virtual Platform x
2.1.1. Agilex™ 5 E-Series Universal Virtual Platform Overview 2.1.2. Agilex™ 5 E-Series Universal Virtual Platform User-Configurable Parameters 2.1.3. Agilex™ 5 E-Series Virtual Platform Key Capabilities
2.1.1. Agilex™ 5 E-Series Universal Virtual Platform Overview x
2.1.1.1. Agilex™ 5 HPS Component 2.1.1.2. HPS Subsystem Component 2.1.1.3. FPGA Fabric Design 2.1.1.4. qsys_top Component 2.1.1.5. FPGA Component 2.1.1.6. Board Component 2.1.1.7. System Component 2.1.1.8. Target Script
2.1.3. Agilex™ 5 E-Series Virtual Platform Key Capabilities x
2.1.3.1. Boot-To-Operating System Prompt 2.1.3.2. Basic Ethernet 2.1.3.3. CPU Power-On and Boot Core Selection 2.1.3.4. Reset Flow 2.1.3.5. General Purpose I/O (GPIO) Loopback 2.1.3.6. USB Disks Hot-Plug Support 2.1.3.7. On-Chip Memory IP FPGA Fabric Example Design 2.1.3.8. FPGA-to-HPS Bridges 2.1.3.9. Exercising Peripheral Subsystem in FPGA Fabric Design 2.1.3.10. USB Controller Host/Device Mode Configuration 2.1.3.11. B0 Silicon Features Selection
3. Agilex™ 5 E-Series Virtual Platform Component Intel® Simics® Models x
3.1. Agilex™ 5 E-Series HPS Intel® Simics® Model 3.2. Virtual Platform HPS Subsystem Components 3.3. Virtual Platform qsys_top Components 3.4. Virtual Platform Board Components 3.5. Modeling Support Limitations
3.1. Agilex™ 5 E-Series HPS Intel® Simics® Model x
3.1.1. Agilex™ 5 E-Series HPS Intel® Simics® Model Architecture 3.1.2. PSS Subsystem Components 3.1.3. MPU and APS Subsystem 3.1.4. MPFE Subsystem 3.1.5. Additional Agilex™ 5 E-Series HPS Components 3.1.6. Agilex™ 5 E-Series B0 Features Support
3.2. Virtual Platform HPS Subsystem Components x
3.2.1. External Memory Interface (EMIF) 3.2.2. Security Device Manager (SDM)
3.3. Virtual Platform qsys_top Components x
3.3.1. FPGA Fabric Peripheral Subsystem On-Chip Memory Example Design FPGA-To-HPS Bridge Memory Spaces
3.4. Virtual Platform Board Components x
3.4.1. Marvel EMAC PHY 3.4.2. SD Card Device 3.4.3. ONFI NAND Memory Device 3.4.4. SPI Flash Device 3.4.5. AT24Cxx EEPROM Device 3.4.6. I3C Device 3.4.7. USB Disk Device 3.4.8. Intel® Simics® Text Console
4. Running a Simulation with the Agilex™ 5 E-Series HPS Model x
4.1. Prerequisites 4.2. Intel® Simics® Simulation Setup for the Agilex™ 5 E-Series Device 4.3. Starting the Simulation 4.4. Getting Device Information from the Intel® Simics® Model
1. About This Document
2. Agilex™ 5 E-Series Intel® Simics® Virtual Platforms
3. Agilex™ 5 E-Series Virtual Platform Component Intel® Simics® Models
4. Running a Simulation with the Agilex™ 5 E-Series HPS Model
5. Supported Use Cases
6. Troubleshooting Issues When Migrating Software from Intel® Simics® to Hardware
A. Document Revision History

3.3.1. FPGA Fabric

Three components integrate the FPGA fabric model:

  • Peripheral subsystem
  • On-Chip memory example design
  • FPGA-To-HPS Bridge memory spaces

The following sections provide additional details about these components:

Peripheral Subsystem

The peripheral subsystem is integrated by the components: button_pio, dipsw_pio, and led_pio. Each one of these components corresponds to the Intel® Simics® model of a parallel input/output core that provides a memory-mapped interface to access general-purpose input/output ports through registers read/write operations. In this case, these cores allow to read the state of a signal connected to a push button or a dip switch and also control the state of an LED. These components are mapped under the lwhps2fpga bridge so the HPS software can get/set the current state of the input/output pin through memory access to the specific location in which these components are mapped.

The mapping of the peripheral subsystem under the lwhps2fpga bridge is shown next:

Table 19.  Peripheral Subsystem Mapping Under the lwhps2fpga Bridge
FPGA Fabric Component Bridge Size Start Address End Address
peripheral subsystem lwhps2fpga 512 MB 0x0020000000 0x003FFFFFFF

The following lines provide more information about the functionality of each one of these components:

  • button_pio : Allows to read the state of a pin connected to a push button. One single pin is supported, and the state of the pin can be read through the DATA register, which is a read-only register. This component supports generating an interrupt that can be connected to the HPS. The interrupt is enabled using the INTERRUPTMASK register by assigning a value of ‘1’. The interrupt is triggered on the rising edge of the input signal.
  • dipsw_pio : Allows to read the state of a pin connected to a dip switch. One single pin is supported, and the state of the pin can be read through the DATA register, which is a read-only register. This component supports generating an interrupt that can be connected to the HPS. The interrupt is enabled using the INTERRUPTMASK register by assigning a value of ‘1’. The interrupt is triggered on the rising edge of the input signal.
  • led_pio : Allows to set the state of a pin connected to an LED. It also allows reading back the state of the pin. Up to 32 pins are supported, and the state of the pins can be set or read through the DATA register (one bit per pin).

The following table shows the internal memory mapping (relative to the address mapping under the lwhps2fpga bridge) of the peripheral components and additional information about the internal registers:

Table 20.  Internal Memory Mapping of the Peripheral Components
Component Mapping Address Range Register Information
Offset Description
button_pio 0x00010060 0x10 0x0 DATA[0:0]- Read state of the button. Read Only.
0x8 INTERRUPTMASK[0:0]- Enable('1’)/Disable('0’) the interrupt trigger. When disable, the interrupt is cleared. Read/Write.
dipsw_pio 0x00010070 0x10 0x0 DATA[0:0]- Read state of the button. Read Only.
0x8 INTERRUPTMASK[0:0]- Enable('1’)/Disable('0’) the interrupt trigger. When disable, the interrupt is cleared. Read/Write.
led_pio 0x00010080 0x10 0x0 DATA[31:0] – Set and read the state of the LEDs. Read/Write.

The registers can be accessed directly using the Intel® Simics® CLI through the write-device-reg, read-device-reg commands or using the offset with the write-device-offset and read-device-offset commands. In the case of the button_pio and dipsw_pio components, the above commands cannot be used to emulate pressing the button or changing the state of the switch since these are input devices. In order to perform this, the following commands can be used: 

# To set the input
simics> @conf.system.board.fpga.soc_inst.periph_subsys.dipsw_pio.port.input_io[0].iface.signal.signal_raise()
simics> @conf.system.board.fpga.soc_inst.periph_subsys.button_pio.port.input_io[0].iface.signal.signal_raise()

# To clear the input
simics> @conf.system.board.fpga.soc_inst.periph_subsys.dipsw_pio.port.input_io[0].iface.signal.signal_lower()

simics> @conf.system.board.fpga.soc_inst.periph_subsys.button_pio.port.input_io[0].iface.signal.signal_lower()

On-Chip Memory Example Design

The On-Chip memory IP allows read/write operations from/to the HPS software connected through the hps2fpga bridge.

The mapping of the On-Chip memory example is defined as follows:

Table 21.  On-Chip Memory Example Mapping

Example Design Name

Bridge

Size

Start Address

End Address
example_design

hps2fpga

1 MB

0x0040000000

0x00400FFFFF

The On-Chip memory example design in the FPGA fabric receives a parameter named base_addr that defines an offset value that indicates the mapping of the instance, taking as reference the Start Address value defined in the previous table.

The objects corresponding to the example design are the following:

  • system.board.fpga.soc_inst.example_design

FPGA-To-HPS Bridge Memory Spaces

Initiators in the FPGA logic model use these memory spaces to start read/write operations directed to the HPS or SDRAM components.

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