Intel® Simics® Simulator for Intel® FPGAs: Agilex™ 5 E-Series Virtual Platform User Guide

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ID 786901
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. About This Document 2. Agilex™ 5 E-Series Intel® Simics® Virtual Platforms 3. Agilex™ 5 E-Series Virtual Platform Component Intel® Simics® Models 4. Running a Simulation with the Agilex™ 5 E-Series HPS Model 5. Supported Use Cases 6. Troubleshooting Issues When Migrating Software from Intel® Simics® to Hardware A. Document Revision History
1. About This Document x
1.1. Terminology 1.2. List of Acronyms
2. Agilex™ 5 E-Series Intel® Simics® Virtual Platforms x
2.1. Agilex™ 5 E-Series Universal Virtual Platform
2.1. Agilex™ 5 E-Series Universal Virtual Platform x
2.1.1. Agilex™ 5 E-Series Universal Virtual Platform Overview 2.1.2. Agilex™ 5 E-Series Universal Virtual Platform User-Configurable Parameters 2.1.3. Agilex™ 5 E-Series Virtual Platform Key Capabilities
2.1.1. Agilex™ 5 E-Series Universal Virtual Platform Overview x
2.1.1.1. Agilex™ 5 HPS Component 2.1.1.2. HPS Subsystem Component 2.1.1.3. FPGA Fabric Design 2.1.1.4. qsys_top Component 2.1.1.5. FPGA Component 2.1.1.6. Board Component 2.1.1.7. System Component 2.1.1.8. Target Script
2.1.3. Agilex™ 5 E-Series Virtual Platform Key Capabilities x
2.1.3.1. Boot-To-Operating System Prompt 2.1.3.2. Basic Ethernet 2.1.3.3. CPU Power-On and Boot Core Selection 2.1.3.4. Reset Flow 2.1.3.5. General Purpose I/O (GPIO) Loopback 2.1.3.6. USB Disks Hot-Plug Support 2.1.3.7. On-Chip Memory IP FPGA Fabric Example Design 2.1.3.8. FPGA-to-HPS Bridges 2.1.3.9. Exercising Peripheral Subsystem in FPGA Fabric Design 2.1.3.10. USB Controller Host/Device Mode Configuration 2.1.3.11. B0 Silicon Features Selection
3. Agilex™ 5 E-Series Virtual Platform Component Intel® Simics® Models x
3.1. Agilex™ 5 E-Series HPS Intel® Simics® Model 3.2. Virtual Platform HPS Subsystem Components 3.3. Virtual Platform qsys_top Components 3.4. Virtual Platform Board Components 3.5. Modeling Support Limitations
3.1. Agilex™ 5 E-Series HPS Intel® Simics® Model x
3.1.1. Agilex™ 5 E-Series HPS Intel® Simics® Model Architecture 3.1.2. PSS Subsystem Components 3.1.3. MPU and APS Subsystem 3.1.4. MPFE Subsystem 3.1.5. Additional Agilex™ 5 E-Series HPS Components 3.1.6. Agilex™ 5 E-Series B0 Features Support
3.2. Virtual Platform HPS Subsystem Components x
3.2.1. External Memory Interface (EMIF) 3.2.2. Security Device Manager (SDM)
3.3. Virtual Platform qsys_top Components x
3.3.1. FPGA Fabric
3.4. Virtual Platform Board Components x
3.4.1. Marvel EMAC PHY 3.4.2. SD Card Device 3.4.3. ONFI NAND Memory Device 3.4.4. SPI Flash Device 3.4.5. AT24Cxx EEPROM Device 3.4.6. I3C Device 3.4.7. USB Disk Device 3.4.8. Intel® Simics® Text Console
4. Running a Simulation with the Agilex™ 5 E-Series HPS Model x
4.1. Prerequisites 4.2. Intel® Simics® Simulation Setup for the Agilex™ 5 E-Series Device 4.3. Starting the Simulation 4.4. Getting Device Information from the Intel® Simics® Model
1. About This Document
2. Agilex™ 5 E-Series Intel® Simics® Virtual Platforms
3. Agilex™ 5 E-Series Virtual Platform Component Intel® Simics® Models
4. Running a Simulation with the Agilex™ 5 E-Series HPS Model
5. Supported Use Cases
6. Troubleshooting Issues When Migrating Software from Intel® Simics® to Hardware
A. Document Revision History

2.1.1.6. Board Component

The board component represents the PCB model containing the Agilex™ 5 E-Series SoC FPGA device and other onboard device components. This component instantiates the FPGA component and the devices controlled by the FPGA component, such as GPIO, Ethernet, SPI, I2C, I3C, and external flash storage devices (NAND, SD Card, QSPI, and USB disks).

The board component is implemented as a Python script named sm_universal_board_comp.py and the hierarchical name of this component is system.board.

The virtual platform board component has the following parameters:

Table 6.  Virtual Platform Board Components
Board Component Parameters Values Defined
USB Disks
  • Two high-speed disks that can be connected to either USB 3.1 Gen 1 or USB 2.0 OTG controller's ports (usb1_typec or usb0_otg ports respectively).

    Maximum disk size 1: 64 TB

    Object: 
    system.board.usbotg_disk
system.board.usb3_hs_disk
  • One SuperSpeed disk that can be connected to USB 3.1 Gen 1 controller port (usb1_typec port). For backwards compatibility, it can also be connected to USB 2.0 OTG controller port (usb0_otg port) although it is not shown when using the auto-completion feature with the plug Intel® Simics® CLI command.

    Maximum disk size1: 64 TB

    Object: 
    system.board.usb3_disk

Marvell PHY

None.

Object: 

system.board.phy0 
system.board.phy1 
system.board.phy2

NAND Flash Device

  • Page Size: 8192 bytes
  • Number of pages per block: 128
  • Bus width: 8 bits
  • Number of Blocks: 4096
  • Spare Page Size: 448 bytes
  • Number of Planes: 1
Object: 
system.board.nand

SD Card Device

Size: 16 GB

Object: 
system.board.sd_card

QSPI Flash Device

  • One instance connected to the SPI0 Host controller.

    Sector Size: 64 x 1024 bytes

    Number of sectors: 4096 

    system.board.spi_flash
  • Once instance connected to the QSPI controller.

    Sector Size: 64 x 1024 bytes

    Number of sectors: 4096

Object: 
system.board.qspi

GPIO Loopback

Implemented GPIO loopback configuration in GPIO0 and GPIO1 ports. In each GPIO port, the pins that are connected are: [0,1], [5,6], [18,19] and [20,21].

Object: 
system.board.gpio_loopback
I3C Devices
Connected to I3C0 instance:

  • pid: 0xFB1122330001 dcr = 0xE1

    inverted_loopback: false

    Object: 
    system.board.i3c0_device1

  • pid: 0xFB1122330002 dcr = 0xE2

    inverted_loopback: false

    Object: 
    system.board.i3c0_device2

  • pid: 0xFB1122330003 dcr = 0xE3

    inverted_loopback: false

    Object: 
    system.board.i3c0_device3
Connected to I3C1 instance:

  • pid: 0xFB1122550001 dcr = 0xC6

    inverted_loopback: false

    Object: 
    system.board.i3c1_device1
I2C EEPROM Devices (AT24Cxx)
  • One instance connected to each one of the I2C controllers (0 to 4).

    Addressing size: 8 bits

    Device Address: 0x54

    Size: 1 KB

    Objects: 
    system.board.eeprom_8b_0
system.board.eeprom_8b_1
system.board.eeprom_8b_2
system.board.eeprom_8b_3
system.board.eeprom_8b_4
  • One instance connected to each one of the I2C controllers (0 to 4).

    Addressing size: 16 bits

    Device Address: 0x50

    Size: 4 KB

    Objects: 
    system.board.eeprom_16b_0
system.board.eeprom_16b_1
system.board.eeprom_16b_2
system.board.eeprom_16b_3
system.board.eeprom_16b_4
  • One instance connected to the I3C0 controller.

    Addressing size: 8 bits

    Device Address: 0x54

    Size: 1 KB

    Objects: 
    system.board.eeprom_8b_i3c0
  • One instance connected to the I3C1 controller.

    Addressing size: 16 bits

    Device Address: 0x50

    Size: 4 KB

    Objects: 
    system.board.eeprom_16b_i3c1

A block diagram of the board component is as follows:

Figure 6. Board Component Block Diagram
1 Actual disk size depends on size of disk image loaded
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