Intel® Simics® Simulator for Intel® FPGAs: Agilex™ 5 E-Series Virtual Platform User Guide

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ID 786901
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. About This Document 2. Agilex™ 5 E-Series Intel® Simics® Virtual Platforms 3. Agilex™ 5 E-Series Virtual Platform Component Intel® Simics® Models 4. Running a Simulation with the Agilex™ 5 E-Series HPS Model 5. Supported Use Cases 6. Troubleshooting Issues When Migrating Software from Intel® Simics® to Hardware A. Document Revision History
1. About This Document x
1.1. Terminology 1.2. List of Acronyms
2. Agilex™ 5 E-Series Intel® Simics® Virtual Platforms x
2.1. Agilex™ 5 E-Series Universal Virtual Platform
2.1. Agilex™ 5 E-Series Universal Virtual Platform x
2.1.1. Agilex™ 5 E-Series Universal Virtual Platform Overview 2.1.2. Agilex™ 5 E-Series Universal Virtual Platform User-Configurable Parameters 2.1.3. Agilex™ 5 E-Series Virtual Platform Key Capabilities
2.1.1. Agilex™ 5 E-Series Universal Virtual Platform Overview x
2.1.1.1. Agilex™ 5 HPS Component 2.1.1.2. HPS Subsystem Component 2.1.1.3. FPGA Fabric Design 2.1.1.4. qsys_top Component 2.1.1.5. FPGA Component 2.1.1.6. Board Component 2.1.1.7. System Component 2.1.1.8. Target Script
2.1.3. Agilex™ 5 E-Series Virtual Platform Key Capabilities x
2.1.3.1. Boot-To-Operating System Prompt 2.1.3.2. Basic Ethernet 2.1.3.3. CPU Power-On and Boot Core Selection 2.1.3.4. Reset Flow 2.1.3.5. General Purpose I/O (GPIO) Loopback 2.1.3.6. USB Disks Hot-Plug Support 2.1.3.7. On-Chip Memory IP FPGA Fabric Example Design 2.1.3.8. FPGA-to-HPS Bridges 2.1.3.9. Exercising Peripheral Subsystem in FPGA Fabric Design 2.1.3.10. USB Controller Host/Device Mode Configuration 2.1.3.11. B0 Silicon Features Selection
3. Agilex™ 5 E-Series Virtual Platform Component Intel® Simics® Models x
3.1. Agilex™ 5 E-Series HPS Intel® Simics® Model 3.2. Virtual Platform HPS Subsystem Components 3.3. Virtual Platform qsys_top Components 3.4. Virtual Platform Board Components 3.5. Modeling Support Limitations
3.1. Agilex™ 5 E-Series HPS Intel® Simics® Model x
3.1.1. Agilex™ 5 E-Series HPS Intel® Simics® Model Architecture 3.1.2. PSS Subsystem Components 3.1.3. MPU and APS Subsystem 3.1.4. MPFE Subsystem 3.1.5. Additional Agilex™ 5 E-Series HPS Components 3.1.6. Agilex™ 5 E-Series B0 Features Support
3.2. Virtual Platform HPS Subsystem Components x
3.2.1. External Memory Interface (EMIF) 3.2.2. Security Device Manager (SDM)
3.3. Virtual Platform qsys_top Components x
3.3.1. FPGA Fabric
3.4. Virtual Platform Board Components x
3.4.1. Marvel EMAC PHY 3.4.2. SD Card Device 3.4.3. ONFI NAND Memory Device 3.4.4. SPI Flash Device 3.4.5. AT24Cxx EEPROM Device 3.4.6. I3C Device 3.4.7. USB Disk Device 3.4.8. Intel® Simics® Text Console
4. Running a Simulation with the Agilex™ 5 E-Series HPS Model x
4.1. Prerequisites 4.2. Intel® Simics® Simulation Setup for the Agilex™ 5 E-Series Device 4.3. Starting the Simulation 4.4. Getting Device Information from the Intel® Simics® Model
1. About This Document
2. Agilex™ 5 E-Series Intel® Simics® Virtual Platforms
3. Agilex™ 5 E-Series Virtual Platform Component Intel® Simics® Models
4. Running a Simulation with the Agilex™ 5 E-Series HPS Model
5. Supported Use Cases
6. Troubleshooting Issues When Migrating Software from Intel® Simics® to Hardware
A. Document Revision History

3.1.2. PSS Subsystem Components

The following table lists the support status of components integrated into the PSS subsystem. The table also indicates any limitation in the component and the object created in the HPS Intel® Simics® model of the Agilex™ 5 E-Series device.

Table 14.  Support Status of Components Integrated into the PSS Subsystem and Their Limitations
Component Supported? Limitations | Objects
PSS NOC

(System Interconnect)

Yes
  • Limitation: Modeled as a memory map with no firewall support.
  • Object: system.board.fpga.soc_inst.hps_subsys.agilex_hps.noc
Clock Manager Yes
  • Limitation: Real functionality is not implemented. CPU runs at a configurable frequency controlled by the hps_cpu_freq_mhz target script parameter and can be set from 400 MHz to 1500 MHz.
  • Object: system.board.fpga.soc_inst.hps_subsys.agilex_hps.clkmgr
Note: If the HPS software reads the clock manager registers to determine the current CPU operation frequency, it leads to a mismatch when compared with the real frequency defined by the parameter (this is observed in U-Boot SPL).
SD/eMMC Host Controller Yes
  • Limitations:
    • ADMA3 DMA mode is not supported.
    • Stop at Block Gap Request feature is not supported.
    • Updating data width using SRS10.EDTW and SRS10.DTW is not supported.
    • Software debug modules are not supported.
    • Hot-plugging of SD card is not supported.
    • Non-DMA mode is not supported.
    • Tested on SD card device with Physical layer version v3.00, and eMMC card with 5.01 electrical standard. Not tested with SDIO cards.
  • Object: system.board.fpga.soc_inst.hps_subsys.agilex_hps.sdmmc
Combo PHY Yes
  • Limitations:
    • This is a skeleton model with very minimalistic features, which include register read/write support.
    • Hot-plugging of SD card is not supported.
  • Object: system.board.fpga.soc_inst.hps_subsys.agilex_hps.combophy
DMA Engines Yes
  • Limitations:
    • Bus locking is not supported.
    • Write back status is not supported.
    • Only single interrupt is supported. Multiple interrupts are not supported for block transfers in case of memory to memory transfers.
  • Objects:
    • system.board.fpga.soc_inst.hps_subsys.agilex_hps.dmac_axi0
    • system.board.fpga.soc_inst.hps_subsys.agilex_hps.dmac_axi1
I3C Controller Yes
  • Limitations:
    • Configured as target has not been tested. The following CCC are not supported in this mode:
      • ENTHDR0 – ENTHDR2
      • GETHDRCAP
      • ENTAS0 – ENTAS3
      • DEFSLVS
      • GETACCMST
      • GETDCR
    • Multimaster mode is not supported.
    • HDR transfers are not supported.
    • CRC/Parity generation and validation is not supported.
  • Objects:
    • system.board.fpga.soc_inst.hps_subsys.agilex_hps.i3c0
    • system.board.fpga.soc_inst.hps_subsys.agilex_hps.i3c1
I2C Controller Yes
  • Limitations:
    • Mixed address mode is not supported.
    • High and ultra-fast speed modes are not supported.
    • 10-bit addressing is not implemented.
    • Master arbitration and start byte are not implemented.
    • SMSBUS is not supported.
    • DMA mode is not implemented.
  • Objects:
    • system.board.fpga.soc_inst.hps_subsys.agilex_hps.i2c0
    • system.board.fpga.soc_inst.hps_subsys.agilex_hps.i2c_slot0
    • system.board.fpga.soc_inst.hps_subsys.agilex_hps.i2c1
    • system.board.fpga.soc_inst.hps_subsys.agilex_hps.i2c_slot1
    • system.board.fpga.soc_inst.hps_subsys.agilex_hps.i2c2
    • system.board.fpga.soc_inst.hps_subsys.agilex_hps.i2c_slot2
    • system.board.fpga.soc_inst.hps_subsys.agilex_hps.i2c3
    • system.board.fpga.soc_inst.hps_subsys.agilex_hps.i2c_slot3
    • system.board.fpga.soc_inst.hps_subsys.agilex_hps.i2c4
    • system.board.fpga.soc_inst.hps_subsys.agilex_hps.i2c_slot4
Pin Mux Control Yes
  • Limitation: This is only a register skeleton model. It does not support implementation to disable access to the peripherals and devices depending on it.
  • Object: system.board.fpga.soc_inst.hps_subsys.agilex_hps.pinmux
USB 3.1 Gen 1 Yes
  • Limitations:
    • Isochronous transfer transactions are not tested.
    • USB Suspend, LPM, Wake up, and Power Control features are not tested.
  • Object: system.board.fpga.soc_inst.hps_subsys.agilex_hps.usb31
USB 2.0 OTG Yes
  • Limitations:
    • SRP functionality is not supported.
    • HNP is a stub model (A- and B-sessions are statically established during connections).
    • FIFO (non-DMA) mode is not supported in device mode.
    • Isochronous USB transfers are not supported.
    • External hubs are not verified.
  • Object: system.board.fpga.soc_inst.hps_subsys.agilex_hps.usb.otg0
Timers Yes Objects:
  • system.board.fpga.soc_inst.hps_subsys.agilex_hps.timer[0]
  • system.board.fpga.soc_inst.hps_subsys.agilex_hps.timer[1]
  • system.board.fpga.soc_inst.hps_subsys.agilex_hps.timer[2]
  • system.board.fpga.soc_inst.hps_subsys.agilex_hps.timer[3]
UART Yes
  • Limitations:
    • AFCE mode is not supported.
    • RTC Flow Control Trigger is not supported.
    • 9-bit data is not supported.
    • Modem control signals are not supported.
    • FIFO Access Mode is not supported.
  • Objects:
    • system.board.fpga.soc_inst.hps_subsys.agilex_hps.uart0
    • system.board.fpga.soc_inst.hps_subsys.agilex_hps.uart1
    • system.board.fpga.soc_inst.hps_subsys.agilex_hps.uart2
GPIO Yes Objects:
  • system.board.fpga.soc_inst.hps_subsys.agilex_hps.gpio0
  • system.board.fpga.soc_inst.hps_subsys.agilex_hps.gpio1
Power Manager Yes
  • Limitations:
    • PSS peripheral SRAM power off is not supported. However, status register is updated as per the register configuration.
    • DSU power management is not supported.
  • Object: system.board.fpga.soc_inst.hps_subsys.agilex_hps.pwrmgr
Reset Manager Yes
  • Limitation:
    • Power-on reset flow from SDM and as a board-level component is not supported.
    • Power-on reset happens only when reset manager is initialized.
    • Watchdog timer can only trigger cold reset from SDM.
    • No debug and trace-related features and signals are supported.
  • Object: system.board.fpga.soc_inst.hps_subsys.agilex_hps.rstmgr
System Manager Yes
  • Limitations:
    • Does not support ECC-related error checks.
    • Does not support the watchdog stop functionality.
    • Control signal interface to SD/eMMC and I3C are not supported.
  • Object: system.board.fpga.soc_inst.hps_subsys.agilex_hps.sysmgr
Watchdog Timer Yes
  • Limitations:
    • Configurable reset pulse length is not supported.
    • Pause mode is not supported.
    • Test mode is not supported.
    • Security-bit disabled for warm and cold reset through SDM is not tested.
  • Objects:
    • system.board.fpga.soc_inst.hps_subsys.agilex_hps.wdt0
    • system.board.fpga.soc_inst.hps_subsys.agilex_hps.wdt1
    • system.board.fpga.soc_inst.hps_subsys.agilex_hps.wdt2
    • system.board.fpga.soc_inst.hps_subsys.agilex_hps.wdt3
    • system.board.fpga.soc_inst.hps_subsys.agilex_hps.wdt4
Ethernet/TSN Yes
  • Limitations:
    • Only basic Ethernet supported by the model.
    • Does not support accessing host Internet (example, ping to google.com).
    • The following features are not supported:
      • VLAN filtering
      • One-step time stamp
      • Multiple queues support in the MAC transaction layer
      • Rx queue to DMA mapping – Dynamic (per packet) mapping
      • Broadcast/multicast packet duplication
      • Receive channel list-based packet duplication.
    • The following features only support register read/write access without any functional behavior:
      • Enhancements to Scheduled Traffic (EST)
      • Frame Preemption (FPE)
      • Time-based scheduling.
      • Data packets transferred at high bit rates may cause CPU stalling. Hence, the HPS Simics model fails to handle Ethernet interrupts that get triggered faster than this component can process. Intel® recommends keeping the data transfer rates below 50 Mbps.
  • Objects:
    • system.board.fpga.soc_inst.hps_subsys.agilex_hps.tsn0
    • system.board.fpga.soc_inst.hps_subsys.agilex_hps.tsn1
    • system.board.fpga.soc_inst.hps_subsys.agilex_hps.tsn2
SPI Controller Yes
  • Limitations:
    • As a host, it does not support the following features:
      • Microwire protocol
      • Execute in Place (XIP)
      • Data Masking
      • Broadcast mode
      • Multimaster
      • Endian conversion
    • As a device, it does not support the following features:
      • Internal DMA
      • Microwire protocol
      • Broadcast mode
      • Endian conversion
  • Objects:
    • Initiator (formerly referred to as master):
      • system.board.fpga.soc_inst.hps_subsys.agilex_hps.spim0
      • system.board.fpga.soc_inst.hps_subsys.agilex_hps.spim1
    • Target (formerly referred to as slave):
      • system.board.fpga.soc_inst.hps_subsys.agilex_hps.spis0
      • system.board.fpga.soc_inst.hps_subsys.agilex_hps.spis1
NAND Controller Yes
  • Limitations:
    • SDR and NV-DDR interfaces are not modeled.
    • ECC protection of flash using BCH codes is not supported.
    • JEDEC device is not supported.
    • Multi-plane operations and cache operations are not supported.
    • Row address remapping is not supported.
  • Object: system.board.fpga.soc_inst.hps_subsys.agilex_hps.nand
On-Chip RAM Yes Object: system.board.fpga.soc_inst.hps_subsys.agilex_hps.ocram
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