F-Tile 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide

ID 720989
Date 11/29/2023
Public
Document Table of Contents

6.7. Reconfiguration Signals

The Ethernet Reconfiguration Interface (reconfig_eth) provides access to the F-Tile Ethernet Hard IP Avalon memory-mapped interface space. This interface is word-addressed. The address always aligns to 32-bit words. the Ethernet reconfiguration register access described in this user guide is byte-based access. You need to convert each word address to a byte address by shifting right by two (dividing by 4). To access individual bytes, use the byte enable signal.

The Transceiver Reconfiguration interface (reconfig_xcvr) provides access to the F-tile transceiver Avalon memory-mapped interface space.

The signals in both Reconfiguration Interfaces are clocked by i_reconfig_clk clock and reset by the i_reconfig_reset signal.

Refer to the F-Tile Ethernet Hard IP User Guide and F-Tile Architecture and PMA and FEC Direct PHY IP User Guide for more information.

Table 21.  Reconfiguration Signals
Signal Name Direction Width Description
Ethernet Reconfiguration Interfaces—synchronous to i_reconfig_clk
i_reconfig_eth_addr Input 14 Address for the Ethernet CSRs (word-addressed).
i_reconfig_eth_read Input 1 Read command for the Ethernet CSRs.
i_reconfig_eth_write Input 1 Write command for the Ethernet CSRs.
i_reconfig_eth_byteenable Input 4 Byte enable for read/write to the Ethernet CSRs.
o_reconfig_eth_readdata Output 32 Read data from reads to the Ethernet CSRs.
o_reconfig_eth_readdata_valid Output 1 Read data from the Ethernet CSRs is valid.
i_reconfig_eth_writedata Input 32 Data for writes to the Ethernet CSRs.
o_reconfig_eth_waitrequest Output 1 Avalon® memory-mapped stalling signal for operations on the Ethernet CSRs.
Transceiver Reconfiguration Interfaces—synchronous to i_reconfig_clk
reconfig_xcvr_slave_0_address Input 18 Address for the transceiver CSRs (word-addressed).
i_reconfig_xcvr0_read Input 1 Read command for the transceiver CSRs.
i_reconfig_xcvr0_write Input 1 Write command for the transceiver CSRs.
i_reconfig_xcvr0_byteenable Input 4 Byte enable for read/write to the transceiver CSRs.
o_reconfig_xcvr0_readdata Output 32 Read data from reads to the transceiver CSRs.
o_reconfig_xcvr0_readdata_valid Output 1 Read data from the transceiver CSRs is valid.
i_reconfig_xcvr0_writedata Input 32 Data for writes to the transceiver CSRs.
o_reconfig_xcvr0_waitrequest Output 1 Avalon® memory-mapped stalling signal for operations on the transceiver CSRs.