F-Tile 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide

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ID 720989
Date 11/29/2023
Public
Document Table of Contents
Document Table of Contents x
1. About the F-Tile 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide 2. 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP Overview 3. Getting Started 4. Functional Description 5. 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP Parameters 6. Interface Signals 7. Configuration Registers 8. F-Tile 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide Archive 9. Document Revision History for the F-Tile 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide
2. 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP Overview x
2.1. Release Information 2.2. Features 2.3. Device Family Support 2.4. Device Speed Grade Support 2.5. Resource Utilization
3. Getting Started x
3.1. Introduction to Intel® FPGA IP 3.2. Installing and Licensing Intel® FPGA IPs 3.3. Specifying the IP Core Parameters and Options 3.4. Generated File Structure 3.5. Simulating Intel® FPGA IPs 3.6. Upgrading the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP Core 3.7. Integrating Your IP Core in Your Design
3.2. Installing and Licensing Intel® FPGA IPs x
3.2.1. Intel® FPGA IP Evaluation Mode
3.7. Integrating Your IP Core in Your Design x
3.7.1. Adding the F-Tile Reference and System PLL IP
4. Functional Description x
4.1. Clocking and Reset Sequence 4.2. Timing Constraints 4.3. Operation Speed Switching 4.4. IEEE 802.3 Clause 37 Auto-Negotiation 4.5. USXGMII 4.6. IEEE 1588 Precision Time Protocol
4.1. Clocking and Reset Sequence x
4.1.1. Clocking 4.1.2. Reset
6. Interface Signals x
6.1. Clock Signals 6.2. Reset Signals 6.3. Serial Interface Signals 6.4. Avalon® Memory-Mapped Interface Signals 6.5. XGMII Signals 6.6. Transceiver Status and Transceiver Clock Status Signals 6.7. Reconfiguration Signals 6.8. Operating Speed and Status Signals
7. Configuration Registers x
7.1. Register Map 7.2. PHY Registers
1. About the F-Tile 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide
2. 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP Overview
3. Getting Started
4. Functional Description
5. 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP Parameters
6. Interface Signals
7. Configuration Registers
8. F-Tile 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide Archive
9. Document Revision History for the F-Tile 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide

9. Document Revision History for the F-Tile 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide

Document Version Intel® Quartus® Prime Version IP Version Changes
2023.11.29 23.3 22.0.0
  • Updated IP version to v22.0.0. Text edits only; no new technical information.
  • Updated the product family name to "Intel Agilex 7."
2022.09.26 22.2 20.1.0
  • Added description for operating_speed in Status Signals table.
  • Grammar and text edits.
  • Renamed 1G/2.5G/5G/10G Multi-rate Ethernet PHY to 1G/2.5G/5G/10G Multirate Ethernet PHY.
2022.06.21 22.2 20.1.0
  • Added PTP feature support for 10M/100M/1G/2.5G/5G/10G (USXGMII) variant
    • Updated Table: Acronym List.
    • Updated the Features topic.
    • Updated the Device Speed Grade Support topic.
    • Updated the Resource Utilization topic.
    • Added a new Topic: IEEE 1588 Precision Time Protocol.
    • Updated Figure: 1G/2.5G/5G/10G Multirate Ethernet PHY IP Parameter Editor.
    • Updated Table: 1G/2.5G/5G/10G Multirate Ethernet PHY Intel FPGA IP Core Parameters.
    • Updated Figure: Interface Signals.
    • Updated Table: Clock Signals.
    • Updated Table: XGMII Signals.
    • Updated Table: Register Map Overview.
    • Updated Table: PHY Registers.
2022.02.23 21.4.1 20.0.0 Initial release.
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