F-Tile 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide

ID 720989
Date 11/29/2023
Public
Document Table of Contents

4. Functional Description

The F-Tile 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP core implements the 10 Mbps to 10 Gbps Ethernet PHY in accordance to the IEEE 802.3 Ethernet standard. The IP handles the frame encapsulation and flow of data between a client logic and Ethernet network via a 10M to 10Gbe PCS and PMA (PHY).

Figure 7. Architecture of the 10M/100M/1G/2.5G/5G/10G (USXGMII) Configuration
In the transmit direction, the PHY encodes the Ethernet frame as required for reliable transmission over the media to the remote end. In the receive direction, the PHY passes frames to the MAC.
Note: You can generate the MAC and PHY design example using the Low Latency Ethernet 10G MAC Intel® FPGA IP Parameter Editor.
The IP core includes the following interfaces:
  • Datapath client-interface:
    • 10M/100M/1G/2.5G/5G/10G (USXGMII) — XGMII, 32 bits
  • Management interface — There are three Avalon memory-mapped slave interfaces for USXGMII management, Ethernet Hard IP, and transceiver reconfigurations.
  • Datapath Ethernet interface:
    • 10M/100M/1G/2.5G/5G/10G (USXGMII) — Single 10.3125 Gbps serial link.
The 10M/100M/1G/2.5G/5G/10G (USXGMII) configuration supports the following features:
  • USXGMII—10M/100M/1G/2.5G/5G/10G speeds
  • Full duplex data transmission only
  • USXGMII Auto-Negotiation