F-Tile 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide

ID 720989
Date 11/29/2023
Public
Document Table of Contents

2.2. Features

Table 4.   1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP Core Features
Feature Description
Operating speeds 10M, 100M, 1G, 2.5G, 5G, and 10G.
MAC-side interface 32-bit XGMII for 10M/100M/1G/2.5G/5G/10G (USXGMII/NBASE-T).
Network-side interface 10.3125 Gbps for 10M/100M/1G/2.5G/5G/10G (USXGMII/NBASE-T).
Avalon® memory-mapped interface Provides access to the configuration registers of the PHY.
PCS function USXGMII PCS for 10M/100M/1G/2.5G/5G/10G (USXGMII).
Auto-negotiation

USXGMII auto-negotiation supported in the 10M/100M/1G/2.5G/5G/10G (USXGMII/NBASE-T) configuration.

IEEE 1588v2
  • Provides the required latency to the MAC if the MAC enables the IEEE 1588v2 feature.
  • Supported in the 10M/100M/1G/2.5G/5G/10G (USXGMII) configuration.
Note: For the 10M/100M/1G/2.5G/5G/10G (USXGMII) configuration, the provided latency is applicable only for 100M, 1G, 2.5G, 5G, and 10G modes.
Sync-E

Provides the clock for Sync-E implementation.