F-Tile 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide

ID 720989
Date 11/29/2023
Public
Document Table of Contents

2. 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP Overview

The 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP for Intel Agilex® 7 F-Tile devices implements the Ethernet protocol as defined in the IEEE 802.3 2005 standard. It consists of a physical coding sublayer (PCS) and an embedded physical media attachment (PMA). You can dynamically switch the PHY operating speed. The IP uses the F-Tile Ethernet hard IP transceiver for serial transmission with soft logic added to implement interface to MAC.
Note: Intel® FPGAs implement and support the required MAC, PHY (PCS and PMA) IP to interface in a chip-to-chip or chip-to-module channel with external NBASE-T PHY standard devices. You must use an external PHY device to drive any copper media.