AN 755: Implementing JESD204B IP Core System Reference Design with ARM HPS As Control Unit (Baremetal Flow)

Download PDF
ID 683776
Date 12/30/2015
Public
Document Table of Contents
Document Table of Contents x
1. Implementing JESD204B IP Core System Reference Design with ARM HPS As Control Unit (Baremetal Flow)
1. Implementing JESD204B IP Core System Reference Design with ARM HPS As Control Unit (Baremetal Flow) x
1.1. Reference Design Overview 1.2. Getting Started 1.3. Reference Design Components 1.4. Reference Design Files 1.5. FPGA Pin Assignments 1.6. System Parameters 1.7. Reference Design Software 1.8. Customizing the Reference Design 1.9. AN 755 Document Revision History
1.2. Getting Started x
1.2.1. Hardware and Software Requirements 1.2.2. Hardware Setup 1.2.3. Compiling the HDL and Programming the Board 1.2.4. Setting up the Software Command Line Environment
1.3. Reference Design Components x
1.3.1. Qsys System 1.3.2. Core PLL 1.3.3. Transport Layer 1.3.4. Test Pattern Generator 1.3.5. Test Pattern Checker
1.3.1. Qsys System x
1.3.1.1. Top Level Qsys Address Map 1.3.1.2. ARM HPS Control Unit and Supporting Processor Peripherals 1.3.1.3. JESD204B Subsystem
1.3.1.2. ARM HPS Control Unit and Supporting Processor Peripherals x
1.3.1.2.1. ARM HPS Control Unit 1.3.1.2.2. FPGA Core Control and Status PIO 1.3.1.2.3. SPI Master Module
1.3.1.3. JESD204B Subsystem x
1.3.1.3.1. JESD204B IP Core 1.3.1.3.2. Reset Sequencer 1.3.1.3.3. Transceiver PHY Reset Controller 1.3.1.3.4. Avalon-MM Bridge 1.3.1.3.5. JESD204B Subsystem Address Map
1.7. Reference Design Software x
1.7.1. User Commands 1.7.2. Dynamic Reconfiguration 1.7.3. Software Interrupt Service Routines (ISR) 1.7.4. Software Parameters 1.7.5. Software Functions Description
1.7.5. Software Functions Description x
1.7.5.1. Functions in main.c Source File 1.7.5.2. Functions in rules.c Source File 1.7.5.3. Custom Peripheral Access Macros in macros.c Source File
1.8. Customizing the Reference Design x
1.8.1. Modifying JESD204B IP Core Parameters 1.8.2. Modifying the Data Rate or Reference Clock Frequency 1.8.3. Implementing a Multi-Link Design
1.8.3. Implementing a Multi-Link Design x
1.8.3.1. Editing the Qsys Project 1.8.3.2. Editing the Top Level HDL File 1.8.3.3. Editing the Software Source Code
1. Implementing JESD204B IP Core System Reference Design with ARM HPS As Control Unit (Baremetal Flow)

1.6. System Parameters

The top level HDL file (jesd204b_ed.sv) includes system parameters that define the configuration of the reference design as a whole. The default values of the parameters are listed in the table below. You can change the values in the HDL file in order to customize the parameters to your system configuration but each parameter value must fall within the specified range as indicated in the table. When modifying the JESD204B IP core-related parameters (L, M, F, N, N_PRIME, S, CS), ensure that the corresponding parameter values in the JESD204B IP core located in the jesd204b_system.qsys Qsys project are set to match the values that you specified in the HDL file. See Modifying JESD204B IP Core Parameters section for more details.

Table 13.  System Parameters

Parameter

Default Value

Supported Values

Description

LINK

1

1, 2, …, n where n is any positive integer

Number of JESD204B links. One link represents one JESD204B instance.

L

4

1, 2, 4, 8

Number of JESD204B lanes per converter device.

M

2

1, 2, 4, 8

Number of JESD204B converters per device.

F

1

1, 2, 4, 8

Number of JESD204B octets per frame.

N

14

12 – 16

Number of JESD204B conversion bits per converter device.

N_PRIME

16

16

Number of JESD204B transmitted bits per sample.

S

1

1, 2

Number of JESD204B transmitted samples per converter device per frame.

CS

0

0 - 3

Number of JESD204B control bits per conversion sample.

F1_FRAMECLK_DIV

4

1, 4

Divider ratio for frame_clk when F=1. Refer to Core PLL section for more details.

F2_FRAMECLK_DIV

2

1, 2

Divider ratio for frame_clk when F=2. Refer to Core PLL section for more details.

POLYNOMIAL_LENGTH

9

7, 9, 15, 23, 31

Defines the polynomial length for the PRBS pattern generator and checker, which is also the equivalent number of stages for the shift register.

  • If PRBS-7 is required, set this parameter to 7.
  • If PRBS-9 is required, set this parameter to 9.
  • If PRBS-15 is required, set this parameter to 15.
  • If PRBS-23 is required, set this parameter to 23.
  • If PRBS-31 is required, set this parameter to 31.

This parameter value must not be larger than N, which is the output data width of the PRBS pattern generator or converter resolution. If an N value of 12-14 is required, PRBS-7 and PRBS-9 are the only feasible options. If an N value of 15-16 is required, PRBS-7, PRBS-9, and PRBS-15 are the only feasible options.

FEEDBACK_TAP

5

6, 5, 14, 18, 28

Defines the feedback tap for the PRBS pattern generator and checker. This is an intermediate stage that is XOR-ed with the last stage to generate to next PRBS bit.

  • If PRBS-7 is required, set this parameter to 6.
  • If PRBS-9 is required, set this parameter to 5.
  • If PRBS-15 is required, set this parameter to 14.
  • If PRBS-23 is required, set this parameter to 18.
  • If PRBS-31 is required, set this parameter to 28.
Related Information
Level Two Title