AN 755: Implementing JESD204B IP Core System Reference Design with ARM HPS As Control Unit (Baremetal Flow)

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ID 683776
Date 12/30/2015
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Document Table of Contents
Document Table of Contents x
1. Implementing JESD204B IP Core System Reference Design with ARM HPS As Control Unit (Baremetal Flow)
1. Implementing JESD204B IP Core System Reference Design with ARM HPS As Control Unit (Baremetal Flow) x
1.1. Reference Design Overview 1.2. Getting Started 1.3. Reference Design Components 1.4. Reference Design Files 1.5. FPGA Pin Assignments 1.6. System Parameters 1.7. Reference Design Software 1.8. Customizing the Reference Design 1.9. AN 755 Document Revision History
1.2. Getting Started x
1.2.1. Hardware and Software Requirements 1.2.2. Hardware Setup 1.2.3. Compiling the HDL and Programming the Board 1.2.4. Setting up the Software Command Line Environment
1.3. Reference Design Components x
1.3.1. Qsys System 1.3.2. Core PLL 1.3.3. Transport Layer 1.3.4. Test Pattern Generator 1.3.5. Test Pattern Checker
1.3.1. Qsys System x
1.3.1.1. Top Level Qsys Address Map 1.3.1.2. ARM HPS Control Unit and Supporting Processor Peripherals 1.3.1.3. JESD204B Subsystem
1.3.1.2. ARM HPS Control Unit and Supporting Processor Peripherals x
1.3.1.2.1. ARM HPS Control Unit 1.3.1.2.2. FPGA Core Control and Status PIO 1.3.1.2.3. SPI Master Module
1.3.1.3. JESD204B Subsystem x
1.3.1.3.1. JESD204B IP Core 1.3.1.3.2. Reset Sequencer 1.3.1.3.3. Transceiver PHY Reset Controller 1.3.1.3.4. Avalon-MM Bridge 1.3.1.3.5. JESD204B Subsystem Address Map
1.7. Reference Design Software x
1.7.1. User Commands 1.7.2. Dynamic Reconfiguration 1.7.3. Software Interrupt Service Routines (ISR) 1.7.4. Software Parameters 1.7.5. Software Functions Description
1.7.5. Software Functions Description x
1.7.5.1. Functions in main.c Source File 1.7.5.2. Functions in rules.c Source File 1.7.5.3. Custom Peripheral Access Macros in macros.c Source File
1.8. Customizing the Reference Design x
1.8.1. Modifying JESD204B IP Core Parameters 1.8.2. Modifying the Data Rate or Reference Clock Frequency 1.8.3. Implementing a Multi-Link Design
1.8.3. Implementing a Multi-Link Design x
1.8.3.1. Editing the Qsys Project 1.8.3.2. Editing the Top Level HDL File 1.8.3.3. Editing the Software Source Code
1. Implementing JESD204B IP Core System Reference Design with ARM HPS As Control Unit (Baremetal Flow)

1.3.1.2. ARM HPS Control Unit and Supporting Processor Peripherals

This section describes the following components:

  • ARM® HPS control unit
  • On-chip memory—provides general purpose data memory to the ARM® HPS
  • System ID (sysid)—a simple read-only device that provides the system with a unique identifier. The ARM® HPS uses this module to verify that an executable program is compiled targeting the actual hardware image configured in the target FPGA.
  • JTAG UART—transmits information between the ARM® HPS and user console
  • External ports parallel I/O (PIO)—provides memory-mapped access to/from the ARM® HPS from/to external ports. There are three external port PIO modules in the system:
    • fpga_dipsw_pio—4-bit input from on-board DIP switches
    • fpga_button_pio—4-bit input from on-board push buttons
    • fpga_led_pio—4-bit output to on-board LEDs
  • FPGA core control and status parallel I/O (PIO)
  • SPI master module
  • Interrupt latency counter (ILC)—measures in clock cycles the time taken from the moment an interrupt request (IRQ) signal is asserted until the interrupt service routine (ISR) begins
  • Avalon-MM bridge—provides single memory-mapped interface between the ARM® HPS lightweight HPS-to-FPGA bridge AXI interface and Avalon-MM peripherals in the FPGA core
  • JTAG-to-Avalon-Master bridge—facilitates System Console interface for debug purposes

Section Content
ARM HPS Control Unit
FPGA Core Control and Status PIO
SPI Master Module

Level Two Title