AN 755: Implementing JESD204B IP Core System Reference Design with ARM HPS As Control Unit (Baremetal Flow)

Download PDF
ID 683776
Date 12/30/2015
Public
Document Table of Contents
Document Table of Contents x
1. Implementing JESD204B IP Core System Reference Design with ARM HPS As Control Unit (Baremetal Flow)
1. Implementing JESD204B IP Core System Reference Design with ARM HPS As Control Unit (Baremetal Flow) x
1.1. Reference Design Overview 1.2. Getting Started 1.3. Reference Design Components 1.4. Reference Design Files 1.5. FPGA Pin Assignments 1.6. System Parameters 1.7. Reference Design Software 1.8. Customizing the Reference Design 1.9. AN 755 Document Revision History
1.2. Getting Started x
1.2.1. Hardware and Software Requirements 1.2.2. Hardware Setup 1.2.3. Compiling the HDL and Programming the Board 1.2.4. Setting up the Software Command Line Environment
1.3. Reference Design Components x
1.3.1. Qsys System 1.3.2. Core PLL 1.3.3. Transport Layer 1.3.4. Test Pattern Generator 1.3.5. Test Pattern Checker
1.3.1. Qsys System x
1.3.1.1. Top Level Qsys Address Map 1.3.1.2. ARM HPS Control Unit and Supporting Processor Peripherals 1.3.1.3. JESD204B Subsystem
1.3.1.2. ARM HPS Control Unit and Supporting Processor Peripherals x
1.3.1.2.1. ARM HPS Control Unit 1.3.1.2.2. FPGA Core Control and Status PIO 1.3.1.2.3. SPI Master Module
1.3.1.3. JESD204B Subsystem x
1.3.1.3.1. JESD204B IP Core 1.3.1.3.2. Reset Sequencer 1.3.1.3.3. Transceiver PHY Reset Controller 1.3.1.3.4. Avalon-MM Bridge 1.3.1.3.5. JESD204B Subsystem Address Map
1.7. Reference Design Software x
1.7.1. User Commands 1.7.2. Dynamic Reconfiguration 1.7.3. Software Interrupt Service Routines (ISR) 1.7.4. Software Parameters 1.7.5. Software Functions Description
1.7.5. Software Functions Description x
1.7.5.1. Functions in main.c Source File 1.7.5.2. Functions in rules.c Source File 1.7.5.3. Custom Peripheral Access Macros in macros.c Source File
1.8. Customizing the Reference Design x
1.8.1. Modifying JESD204B IP Core Parameters 1.8.2. Modifying the Data Rate or Reference Clock Frequency 1.8.3. Implementing a Multi-Link Design
1.8.3. Implementing a Multi-Link Design x
1.8.3.1. Editing the Qsys Project 1.8.3.2. Editing the Top Level HDL File 1.8.3.3. Editing the Software Source Code
1. Implementing JESD204B IP Core System Reference Design with ARM HPS As Control Unit (Baremetal Flow)

1.3.1.2.2. FPGA Core Control and Status PIO

The FPGA core control and status PIO modules provide general purpose I/O access to and from the ARM® HPS for elements inside the FPGA core fabric. The FPGA control PIO is a 32-bit output signal from the ARM® HPS to the FPGA core fabric. The FPGA status PIO is a 32-bit input signal from the FPGA core fabric to the ARM® HPS. The signal connectivity is set at the top level HDL file. The tables below describe the signal connectivity for the FPGA control and status registers.

Table 5.  Signal Connectivity for FPGA Control Registers

Bit

Signal

0

RX serial loopback enable for lane 0 (Link 0)

1

RX serial loopback enable for lane 1 (Link 0)

2

RX serial loopback enable for lane 2 (Link 0)

3

RX serial loopback enable for lane 3 (Link 0)

4-30

RX serial loopback enable for subsequent links, if present

31

Sysref

Table 6.  Signal Connectivity for FPGA Status Registers

Bit

Signal

0

Core PLL locked

1

TX transceiver ready (Link 0)

2

RX transceiver ready (Link 0)

3

Test pattern checker data error (Link 0)

4-31

TX transceiver ready, RX transceiver ready, and test pattern checker data error signals for subsequent links, if present

Level Two Title