AN 755: Implementing JESD204B IP Core System Reference Design with ARM HPS As Control Unit (Baremetal Flow)

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ID 683776
Date 12/30/2015
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Document Table of Contents
Document Table of Contents x
1. Implementing JESD204B IP Core System Reference Design with ARM HPS As Control Unit (Baremetal Flow)
1. Implementing JESD204B IP Core System Reference Design with ARM HPS As Control Unit (Baremetal Flow) x
1.1. Reference Design Overview 1.2. Getting Started 1.3. Reference Design Components 1.4. Reference Design Files 1.5. FPGA Pin Assignments 1.6. System Parameters 1.7. Reference Design Software 1.8. Customizing the Reference Design 1.9. AN 755 Document Revision History
1.2. Getting Started x
1.2.1. Hardware and Software Requirements 1.2.2. Hardware Setup 1.2.3. Compiling the HDL and Programming the Board 1.2.4. Setting up the Software Command Line Environment
1.3. Reference Design Components x
1.3.1. Qsys System 1.3.2. Core PLL 1.3.3. Transport Layer 1.3.4. Test Pattern Generator 1.3.5. Test Pattern Checker
1.3.1. Qsys System x
1.3.1.1. Top Level Qsys Address Map 1.3.1.2. ARM HPS Control Unit and Supporting Processor Peripherals 1.3.1.3. JESD204B Subsystem
1.3.1.2. ARM HPS Control Unit and Supporting Processor Peripherals x
1.3.1.2.1. ARM HPS Control Unit 1.3.1.2.2. FPGA Core Control and Status PIO 1.3.1.2.3. SPI Master Module
1.3.1.3. JESD204B Subsystem x
1.3.1.3.1. JESD204B IP Core 1.3.1.3.2. Reset Sequencer 1.3.1.3.3. Transceiver PHY Reset Controller 1.3.1.3.4. Avalon-MM Bridge 1.3.1.3.5. JESD204B Subsystem Address Map
1.7. Reference Design Software x
1.7.1. User Commands 1.7.2. Dynamic Reconfiguration 1.7.3. Software Interrupt Service Routines (ISR) 1.7.4. Software Parameters 1.7.5. Software Functions Description
1.7.5. Software Functions Description x
1.7.5.1. Functions in main.c Source File 1.7.5.2. Functions in rules.c Source File 1.7.5.3. Custom Peripheral Access Macros in macros.c Source File
1.8. Customizing the Reference Design x
1.8.1. Modifying JESD204B IP Core Parameters 1.8.2. Modifying the Data Rate or Reference Clock Frequency 1.8.3. Implementing a Multi-Link Design
1.8.3. Implementing a Multi-Link Design x
1.8.3.1. Editing the Qsys Project 1.8.3.2. Editing the Top Level HDL File 1.8.3.3. Editing the Software Source Code
1. Implementing JESD204B IP Core System Reference Design with ARM HPS As Control Unit (Baremetal Flow)

1.8.1. Modifying JESD204B IP Core Parameters

To customize the JESD204B IP core parameters to meet your specifications, follow these steps:

  1. Launch the Quartus® Prime software.
  2. On the File menu, click Open.
  3. Browse and select the jesd204b_ed_soc.qsys file located in the project directory.
  4. Click Open to view the Qsys system in the System Contents window.
  5. Right-click on the jesd204b_subsystem_0 module and select the Drill into subsystem option. The jesd204b_system.qsys project opens in the System Contents window.
  6. In the System Contents window, locate the jesd204b module and double-click it to open the parameter editor. This brings up the Parameters tab that shows the current parameter settings of the JESD204B IP core.
  7. Modify the IP core parameters of the jesd204b module as necessary per your system specifications. When you are done, navigate to File and click Save.
  8. Click the Move to the top of hierarchy button to move back to the jesd204b_ed_soc.qsys view.
  9. Click Generate HDL to generate the HDL files needed for Quartus compilation.
  10. After the HDL generation completes, click Finish to save your Qsys settings and exit the Qsys window.
  11. You have to manually change the system parameters in the top level HDL file to match the parameters that you set in the Qsys project (if applicable). Open the top level HDL file (jesd204b_ed.sv) in any text editor of your choice.
  12. Modify the system parameters at the top of the file to match the new JESD204B IP core settings in the Qsys project, if applicable. Refer to the System Parameters section for more details on the system parameters.
  13. Save the file and compile the design in Quartus as per the instructions in the Compiling the HDL and Programming the Board section.
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