AN 755: Implementing JESD204B IP Core System Reference Design with ARM HPS As Control Unit (Baremetal Flow)

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ID 683776
Date 12/30/2015
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Document Table of Contents
Document Table of Contents x
1. Implementing JESD204B IP Core System Reference Design with ARM HPS As Control Unit (Baremetal Flow)
1. Implementing JESD204B IP Core System Reference Design with ARM HPS As Control Unit (Baremetal Flow) x
1.1. Reference Design Overview 1.2. Getting Started 1.3. Reference Design Components 1.4. Reference Design Files 1.5. FPGA Pin Assignments 1.6. System Parameters 1.7. Reference Design Software 1.8. Customizing the Reference Design 1.9. AN 755 Document Revision History
1.2. Getting Started x
1.2.1. Hardware and Software Requirements 1.2.2. Hardware Setup 1.2.3. Compiling the HDL and Programming the Board 1.2.4. Setting up the Software Command Line Environment
1.3. Reference Design Components x
1.3.1. Qsys System 1.3.2. Core PLL 1.3.3. Transport Layer 1.3.4. Test Pattern Generator 1.3.5. Test Pattern Checker
1.3.1. Qsys System x
1.3.1.1. Top Level Qsys Address Map 1.3.1.2. ARM HPS Control Unit and Supporting Processor Peripherals 1.3.1.3. JESD204B Subsystem
1.3.1.2. ARM HPS Control Unit and Supporting Processor Peripherals x
1.3.1.2.1. ARM HPS Control Unit 1.3.1.2.2. FPGA Core Control and Status PIO 1.3.1.2.3. SPI Master Module
1.3.1.3. JESD204B Subsystem x
1.3.1.3.1. JESD204B IP Core 1.3.1.3.2. Reset Sequencer 1.3.1.3.3. Transceiver PHY Reset Controller 1.3.1.3.4. Avalon-MM Bridge 1.3.1.3.5. JESD204B Subsystem Address Map
1.7. Reference Design Software x
1.7.1. User Commands 1.7.2. Dynamic Reconfiguration 1.7.3. Software Interrupt Service Routines (ISR) 1.7.4. Software Parameters 1.7.5. Software Functions Description
1.7.5. Software Functions Description x
1.7.5.1. Functions in main.c Source File 1.7.5.2. Functions in rules.c Source File 1.7.5.3. Custom Peripheral Access Macros in macros.c Source File
1.8. Customizing the Reference Design x
1.8.1. Modifying JESD204B IP Core Parameters 1.8.2. Modifying the Data Rate or Reference Clock Frequency 1.8.3. Implementing a Multi-Link Design
1.8.3. Implementing a Multi-Link Design x
1.8.3.1. Editing the Qsys Project 1.8.3.2. Editing the Top Level HDL File 1.8.3.3. Editing the Software Source Code
1. Implementing JESD204B IP Core System Reference Design with ARM HPS As Control Unit (Baremetal Flow)

1.5. FPGA Pin Assignments

The interface ports of the top level HDL file (jesd204b_ed.sv) with their corresponding FPGA pin assignments on the Arria V SoC development board are listed in the table below. The table only lists the JESD204B-related pin assignments. For all other board-related and ARM HPS-related pin assignments, refer to the Quartus settings file (jesd204b_ed.qsf).

Table 12.  FPGA Pin Assignments on Arria V SoC Development Board
Interface Port Name FPGA Pin Number I/O Standard Direction Board Source/Destination Description
General Clocks
fpga_clk_50 AU32 1.5 V Input 50 MHz on-board oscillator (X4) via SL18860DC clock distribution buffer (U30) Reference clock for ARM HPS control unit and all peripherals connected via AXI/Avalon-MM interconnect. The clock frequency is 50 MHz.
device_clk

AC31 1

U31 2

LVDS Input

FMC Port A connector 1

Si571 Programmable Oscillator 2

Reference clock for JESD204B data path. The clock frequency is 153.6 MHz
device_clk (n)

AC32 1

U32 2

LVDS Input

FMC Port A connector 1

Si571 Programmable Oscillator 2

Serial Data
jesd204_rx_serial_data[3] AB39 1.5 V PCML Input

FMC Port A connector

 Differential high speed serial input data.
jesd204_rx_serial_data[3] (n) AB38 Input

FMC Port A connector
jesd204_rx_serial_data[2] AF39 Input

FMC Port A connector
jesd204_rx_serial_data[2] (n) AF38 Input

FMC Port A connector
jesd204_rx_serial_data[1] Y39 Input

FMC Port A connector
jesd204_rx_serial_data[1] (n) Y38 Input

FMC Port A connector
jesd204_rx_serial_data[0] T39 Input

FMC Port A connector
jesd204_rx_serial_data[0] (n) T38 Input FMC Port A connector
jesd204_tx_serial_data[3] AA37 1.5 V PCML Output

FMC Port A connector

 Differential high speed serial output data.
jesd204_tx_serial_data[3] (n) AA36 Output

FMC Port A connector
jesd204_tx_serial_data[2] AE37 Output

FMC Port A connector
jesd204_tx_serial_data[2] (n) AE36 Output

FMC Port A connector
jesd204_tx_serial_data[1] W37 Output

FMC Port A connector
jesd204_tx_serial_data[1] (n) W36 Output

FMC Port A connector
jesd204_tx_serial_data[0] R37 Output

FMC Port A connector
jesd204_tx_serial_data[0] (n) R36 Output

FMC Port A connector
JESD204B Control Signals
jesd204_sysref_out E27 LVDS Output

FMC Port A connector

 SYSREF signal for JESD204B Subclass 1 implementation.
jesd204_sysref_out (n) F27 LVDS Output

FMC Port A connector
jesd204_sync_n_out J26 LVDS Output

FMC Port A connector

 Indicates a SYNC_N from the receiver. This is an active low signal and is asserted 0 to indicate a synchronization request or error reporting.
jesd204_sync_n_out (n) K26 LVDS Output

FMC Port A connector
SPI
spi_MISO H27 2.5 V Input

FMC Port A connector

 Output data from a slave to the input of the master
spi_MOSI N23 2.5 V Output

FMC Port A connector

 Output data from the master to the inputs of the slaves.
spi_SCLK M23 2.5 V Output

FMC Port A connector

 Clock driven by the master to slaves, to synchronize the data bits.
spi_SS_n[0] P27 2.5 V Output

FMC Port A connector

 Active low select signal driven by the master to individual slaves, to select the target slave.
Interface Port Name FPGA Pin Number I/O Standard Direction Description
Avalon-ST User Data 3
jesd204_avst_usr_din [LINK* TL_DATA_BUS_WIDTH-1:0] — — Input TX data from the Avalon-ST source interface. The TL_DATA_BUS_WIDTH is determined by the following formulas:
  • If F = 1, TL_DATA_BUS_WIDTH = F1_FRAMECLK_DIV*8*1*L*N/N_PRIME
  • If F = 2, TL_DATA_BUS_WIDTH = F2_FRAMECLK_DIV*8*2*L*N/N_PRIME
  • If F = 4, TL_DATA_BUS_WIDTH = 8*4*L*N/N_PRIME
  • If F = 8, TL_DATA_BUS_WIDTH = 8*8*L*N/N_PRIME
jesd204_avst_usr_din_valid [LINK-1:0] — — Input Indicates whether data from the Avalon-ST source interface to the transport layer is valid or invalid.
  • 0: data is invalid
  • 1: data is valid
jesd204_avst_usr_din_ready [LINK-1:0] — — Output Indicates that the transport layer is ready to accept data from the Avalon-ST source interface.
  • 0: transport layer is not ready to receive data
  • 1: transport layer is ready to receive data
jesd204_avst_usr_dout [LINK*TL_DATA_BUS_WIDTH-1:0] — — Output RX data to the Avalon-ST sink interface. The TL_DATA_BUS_WIDTH is determined by the following formulas:
  • If F = 1, TL_DATA_BUS_WIDTH = F1_FRAMECLK_DIV*8*1*L*N/N_PRIME
  • If F = 2, TL_DATA_BUS_WIDTH = F2_FRAMECLK_DIV*8*2*L*N/N_PRIME
  • If F = 4, TL_DATA_BUS_WIDTH = 8*4*L*N/N_PRIME
  • If F = 8, TL_DATA_BUS_WIDTH = 8*8*L*N/N_PRIME
jesd204_avst_usr_dout_valid [LINK-1:0] — — Output Indicates whether the data from the transport layer to the Avalon-ST sink interface is valid or invalid.
  • 0: data is invalid
  • 1: data is valid
jesd204_avst_usr_dout_ready [LINK-1:0] — — Input Indicates that the Avalon-ST sink interface is ready to accept data from the transport layer.
  • 0: Avalon-ST sink interface is not ready to receive data
  • 1: Avalon-ST sink interface is ready to receive data
jesd204_avst_patchk_data_error [LINK-1:0] — — Output Output signal from pattern checker indicating a pattern check error.
1 For external converter interoperation.
2 For internal serial loopback only.
3 The Avalon-ST user data signals are classified as virtual pins and are not explicitly assigned to actual pins. You are expected to connect the signals to the rest of your design.
Level Two Title