Intel® Stratix® 10 Device Datasheet

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ID 683181
Date 12/08/2023
Public
Document Table of Contents
Document Table of Contents x
Intel® Stratix® 10 Device Datasheet
Intel® Stratix® 10 Device Datasheet x
Electrical Characteristics Switching Characteristics Configuration Specifications I/O Timing Programmable IOE Delay Glossary Document Revision History for the Intel® Stratix® 10 Device Datasheet
Electrical Characteristics x
Operating Conditions
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot and Undershoot Voltage Recommended Operating Conditions DC Characteristics I/O Standard Specifications
Recommended Operating Conditions x
Recommended Operating Conditions Transceiver Power Supply Operating Conditions HPS Power Supply Operating Conditions
DC Characteristics x
Supply Current and Power Consumption I/O Pin Leakage Current Bus Hold Specifications OCT Calibration Accuracy Specifications OCT Without Calibration Resistance Tolerance Specifications Pin Capacitance Internal Weak Pull-Up Resistor
I/O Standard Specifications x
Single-Ended I/O Standards Specifications Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications Differential SSTL I/O Standards Specifications Differential HSTL and HSUL I/O Standards Specifications Differential I/O Standards Specifications
Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications x
Differential POD12 Standards Specifications
Switching Characteristics x
Core Performance Specifications Periphery Performance Specifications L-Tile Transceiver Performance Specifications H-Tile Transceiver Performance Specifications E-Tile Transceiver Performance Specifications P-Tile Transceiver Performance Specifications HPS Performance Specifications
Core Performance Specifications x
Clock Tree Specifications PLL Specifications DSP Block Specifications Memory Block Specifications Direct Interface Bus (DIB) Specifications Internal Temperature Sensing Diode Specifications External Temperature Sensing Diode Specifications Internal Voltage Sensor Specifications
PLL Specifications x
Fractional PLL Specifications I/O PLL Specifications
Periphery Performance Specifications x
High-Speed I/O Specifications DPA Lock Time Specifications LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specifications Memory Standards Supported by the Hard Memory Controller Memory Standards Supported by the Soft Memory Controller Memory Standards Supported by the HPS Hard Memory Controller DLL Range Specifications Memory Output Clock Jitter Specifications Performance Specifications of the HBM2 Interface in Intel® Stratix® 10 MX, NX, and DX 2100 Devices HBM2 Interface Performance OCT Calibration Block Specifications
L-Tile Transceiver Performance Specifications x
Transceiver Performance for Intel® Stratix® 10 L-Tile Devices Transceiver Specifications for Intel® Stratix® 10 L-Tile Devices
H-Tile Transceiver Performance Specifications x
Transceiver Performance for Intel® Stratix® 10 H-Tile Devices Transceiver Specifications for Intel® Stratix® 10 H-Tile Devices
E-Tile Transceiver Performance Specifications x
Transceiver Performance for Intel® Stratix® 10 E-Tile Devices Transceiver Reference Clock Specifications Transmitter Specifications for Intel® Stratix® 10 E-Tile Devices Receiver Specifications for Intel® Stratix® 10 E-Tile Devices
P-Tile Transceiver Performance Specifications x
Transceiver Performance for Intel® Stratix® 10 DX P-Tile Devices Transceiver Reference Clock Specifications Transmitter Specification for Intel® Stratix® 10 DX P-Tile Devices Receiver Specifications for Intel® Stratix® 10 DX P-Tile Devices
HPS Performance Specifications x
HPS Clock Performance HPS Internal Oscillator Frequency HPS PLL Specifications HPS Cold Reset HPS SPI Timing Characteristics HPS SD/MMC Timing Characteristics HPS USB UPLI Timing Characteristics HPS Ethernet Media Access Controller (EMAC) Timing Characteristics HPS I2C Timing Characteristics HPS NAND Timing Characteristics HPS Trace Timing Characteristics HPS GPIO Interface HPS JTAG Timing Characteristics HPS Programmable I/O Timing Characteristics
HPS PLL Specifications x
HPS PLL Input Requirements HPS PLL Performance
Configuration Specifications x
General Configuration Timing Specifications POR Specifications External Configuration Clock Source Requirements JTAG Configuration Timing AS Configuration Timing Avalon® -ST Configuration Timing Configuration Bit Stream Sizes
Intel® Stratix® 10 Device Datasheet

Recommended Operating Conditions

Table 7.  Recommended Operating Conditions for Intel® Stratix® 10 DevicesThis table lists the steady-state voltage values expected for Intel® Stratix® 10 devices. Power supply ramps must all be strictly monotonic, without plateaus.
Symbol Description Condition Minimum 8 Typical Maximum 8 Unit
VCC Core voltage power supply for Intel® Stratix® 10 GX 10M device –E2L, –C2L 0.85 0.88 0.91 V
Core voltage power supply for all other Intel® Stratix® 10 devices –E1V, –I1V, –E2V, –I2V, –E3V, –I3V 9 (Typical) – 30 mV 0.8 – 0.94 (Typical) + 30 mV V
–E2L, –I2L, –E3X, –I3X 0.82 0.85 0.88 V
VCCP Periphery circuitry and transceiver fabric interface power supply for Intel® Stratix® 10 GX 10M device –E2L, –C2L 0.85 0.88 0.91 V
Periphery circuitry and transceiver fabric interface power supply for all other Intel® Stratix® 10 devices –E1V, –I1V, –E2V, –I2V, –E3V, –I3V 9 (Typical) – 30 mV 0.8 – 0.94 (Typical) + 30 mV V
–E2L, –I2L, –E3X, –I3X 0.82 0.85 0.88 V
VCCIO_SDM Configuration pins power supply 1.8 V 1.71 1.8 1.89 V
VCCPLLDIG_SDM Secure Device Manager (SDM) block PLL digital power supply — 0.87 0.9 0.93 V
VCCPLL_SDM SDM block PLL analog power supply — 1.71 1.8 1.89 V
VCCFUSEWR_SDM Fuse block writing power supply — 2.35 2.4 2.45 V
VCCADC ADC voltage sensor power supply — 1.71 1.8 1.89 V
VCCERAM Embedded memory and digital transceiver power supply 0.9 V 0.87 0.9 0.93 V
VCCBAT 10 Battery back-up power supply (For design security volatile key register) — 1.2 — 1.8 V
VCCPT Power supply for programmable regulator and I/O pre-driver 1.8 V 1.71 1.8 1.89 V
VCCIO I/O buffers power supply for LVDS I/O (except for 1SG040HF35 and 1SX040HF35 banks 3C and 3D) 1.8 V 1.71 1.8 1.89 V
1.5 V 1.425 1.5 1.575 V
1.35 V 1.283 1.35 1.45 V
1.25 V 1.19 1.25 1.31 V
1.2 V 1.14 1.2 1.26 V
VCCIO3V I/O buffers power supply for 3 V I/O 3.0 V 2.85 3 3.15 V
2.5 V 2.375 2.5 2.625 V
1.8 V 1.71 1.8 1.89 V
1.5 V 1.425 1.5 1.575 V
1.2 V 1.14 1.2 1.26 V
VCCIO3C I/O buffers power supply for 1SG040HF35 and 1SX040HF35 devices bank 3C only 3.3 V 3.135 3.3 3.465 V
3.0 V 2.85 3 3.15 V
VCCIO3D I/O buffers power supply for 1SG040HF35 and 1SX040HF35 devices bank 3D only 1.8 V 1.71 1.8 1.89 V
VCCIO_UIB Power supply for the Universal Interface Bus between the core and embedded HBM2 memory 1.2 V 1.17 1.2 1.23 V
VCCM_WORD Power supply for the embedded HBM2 memory — 2.4 2.5 2.6 V
VCCA_PLL PLL analog voltage regulator power supply — 1.71 1.8 1.89 V
VI 11 12 DC input voltage 3.3 V I/O –0.3 — VCCIO + 0.33 V
3 V I/O –0.3 — VCCIO + 0.65 V
LVDS I/O –0.3 — VCCIO + 0.3 V
VO Output voltage — 0 — VCCIO V
TJ Operating junction temperature for Intel® Stratix® 10 MX, NX, and DX 2100 devices Extended 13 0 — 100 14 °C
Operating junction temperature for Intel® Stratix® 10 GX 10M device Commercial 25 — 85 °C
Extended 0 — 100 °C
Operating junction temperature for all other Intel® Stratix® 10 devices Extended 0 — 100 15 °C
Industrial –40 (–20 for E-tile devices) 16 — 10015 °C
tRAMP 17 18 19 Power supply ramp time Standard POR 200 μs — 100 ms —
Related Information
8 This value describes the required voltage measured between the PCB power and ground ball during normal device operation. The voltage ripple includes both regulator DC ripple and the dynamic noise. Refer to power distribution network (PDN) tool for PCB power distribution network design.
9 The use of Power Management Bus (PMBus*) voltage regulator dedicated to Intel® Stratix® 10 SmartVID devices is mandatory for VCC and VCCP. The PMBus* voltage regulator and Intel® Stratix® 10 SmartVID devices are connected via PMBus*.
10 Intel recommends connecting VCCBAT to a 1.8 V power supply if you do not use the design security feature in Intel® Stratix® 10 devices.
11 The LVDS I/O values are applicable to all dedicated and dual-function configuration I/Os.
12 This value applies to both input and tri-stated output configuration. Pin voltage should not be externally pulled higher than the maximum value.
13 Intel® Stratix® 10 MX, NX, and DX 2100 devices are generally offered in Extended temperature range only. If Industrial temperature range is required, note that you can configure these devices at less than 0°C, but the HBM2 interface is held in reset and is not calibrated until TJ reaches 0°C. Contact your Intel sales representative for the availability of Intel® Stratix® 10 MX, NX, and DX 2100 Industrial temperature range devices.
14 Recommended maximum operating temperature for HBM2 is 95°C.
15 For Intel® Stratix® 10 GX, SX, TX, and DX, the temperature excursion of these devices is allowed to operate between 100°C and 110°C for short periods of time. For more information, refer to AN 950: Temperature Excursions for Intel® Stratix® 10 and Intel Agilex® 7 F-Series Device Families.
16 E-tile supports an operating temperature range of –40°C to 100°C. However, the E-tile transceivers may experience a higher error rate from –40°C to –20°C because of the calibration procedure when starting at a low temperature. Therefore, the recommended operating temperature range for E-tile protocol-compliant transceiver links is –20°C to 100°C. The environmental temperature ramp rate for the device is limited to 2°C per minute, otherwise, the device would not be compliant and may lead to link activity failure.
17 tRAMP is the ramp time of each individual power supply, not the ramp time of all combined power supplies.
18 To support AS fast mode, all power supplies to the Intel® Stratix® 10 device must be fully ramped-up within 10 ms to the recommended operating conditions.
19 To support AS normal mode, VCCIO_SDM of the Intel® Stratix® 10 device must be fully ramped-up within 10 ms to the recommended operating condition.
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