Intel® Stratix® 10 Device Datasheet

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ID 683181
Date 12/08/2023
Public
Document Table of Contents
Document Table of Contents x
Intel® Stratix® 10 Device Datasheet
Intel® Stratix® 10 Device Datasheet x
Electrical Characteristics Switching Characteristics Configuration Specifications I/O Timing Programmable IOE Delay Glossary Document Revision History for the Intel® Stratix® 10 Device Datasheet
Electrical Characteristics x
Operating Conditions
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot and Undershoot Voltage Recommended Operating Conditions DC Characteristics I/O Standard Specifications
Recommended Operating Conditions x
Recommended Operating Conditions Transceiver Power Supply Operating Conditions HPS Power Supply Operating Conditions
DC Characteristics x
Supply Current and Power Consumption I/O Pin Leakage Current Bus Hold Specifications OCT Calibration Accuracy Specifications OCT Without Calibration Resistance Tolerance Specifications Pin Capacitance Internal Weak Pull-Up Resistor
I/O Standard Specifications x
Single-Ended I/O Standards Specifications Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications Differential SSTL I/O Standards Specifications Differential HSTL and HSUL I/O Standards Specifications Differential I/O Standards Specifications
Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications x
Differential POD12 Standards Specifications
Switching Characteristics x
Core Performance Specifications Periphery Performance Specifications L-Tile Transceiver Performance Specifications H-Tile Transceiver Performance Specifications E-Tile Transceiver Performance Specifications P-Tile Transceiver Performance Specifications HPS Performance Specifications
Core Performance Specifications x
Clock Tree Specifications PLL Specifications DSP Block Specifications Memory Block Specifications Direct Interface Bus (DIB) Specifications Internal Temperature Sensing Diode Specifications External Temperature Sensing Diode Specifications Internal Voltage Sensor Specifications
PLL Specifications x
Fractional PLL Specifications I/O PLL Specifications
Periphery Performance Specifications x
High-Speed I/O Specifications DPA Lock Time Specifications LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specifications Memory Standards Supported by the Hard Memory Controller Memory Standards Supported by the Soft Memory Controller Memory Standards Supported by the HPS Hard Memory Controller DLL Range Specifications Memory Output Clock Jitter Specifications Performance Specifications of the HBM2 Interface in Intel® Stratix® 10 MX, NX, and DX 2100 Devices HBM2 Interface Performance OCT Calibration Block Specifications
L-Tile Transceiver Performance Specifications x
Transceiver Performance for Intel® Stratix® 10 L-Tile Devices Transceiver Specifications for Intel® Stratix® 10 L-Tile Devices
H-Tile Transceiver Performance Specifications x
Transceiver Performance for Intel® Stratix® 10 H-Tile Devices Transceiver Specifications for Intel® Stratix® 10 H-Tile Devices
E-Tile Transceiver Performance Specifications x
Transceiver Performance for Intel® Stratix® 10 E-Tile Devices Transceiver Reference Clock Specifications Transmitter Specifications for Intel® Stratix® 10 E-Tile Devices Receiver Specifications for Intel® Stratix® 10 E-Tile Devices
P-Tile Transceiver Performance Specifications x
Transceiver Performance for Intel® Stratix® 10 DX P-Tile Devices Transceiver Reference Clock Specifications Transmitter Specification for Intel® Stratix® 10 DX P-Tile Devices Receiver Specifications for Intel® Stratix® 10 DX P-Tile Devices
HPS Performance Specifications x
HPS Clock Performance HPS Internal Oscillator Frequency HPS PLL Specifications HPS Cold Reset HPS SPI Timing Characteristics HPS SD/MMC Timing Characteristics HPS USB UPLI Timing Characteristics HPS Ethernet Media Access Controller (EMAC) Timing Characteristics HPS I2C Timing Characteristics HPS NAND Timing Characteristics HPS Trace Timing Characteristics HPS GPIO Interface HPS JTAG Timing Characteristics HPS Programmable I/O Timing Characteristics
HPS PLL Specifications x
HPS PLL Input Requirements HPS PLL Performance
Configuration Specifications x
General Configuration Timing Specifications POR Specifications External Configuration Clock Source Requirements JTAG Configuration Timing AS Configuration Timing Avalon® -ST Configuration Timing Configuration Bit Stream Sizes
Intel® Stratix® 10 Device Datasheet

HPS SPI Timing Characteristics

Table 84.  SPI Master Timing Requirements for Intel® Stratix® 10 DevicesYou can adjust the input delay timing by programming the rx_sample_dly register.
Symbol Description Min Typ Max Unit
Tspi_ref_clk The period of the SPI internal reference clock, sourced from l4_main_clk 2.5 — — ns
Tclk SPIM_CLK clock period 16.67 — — ns
Tdutycycle SPIM_CLK duty cycle 45 50 55 %
Tck_jitter SPIM_CLK output jitter — — 2 %
Tdio Master-out slave-in (MOSI) output skew –3 — 2 ns
Tdssfrst 140 SPI_SS_N asserted to first SPIM_CLK edge (1.5 × Tclk) – 2 — — ns
Tdsslst 140 Last SPIM_CLK edge to SPI_SS_N deasserted Tclk – 2 — — ns
Tsu 141 SPIM_MISO setup time with respect to SPIM_CLK capture edge 4.5 – (rx_sample_dly × T spi_ref_clk) 142 — — ns
Th 141 Input hold in respect to SPIM_CLK capture edge 1.3 + (rx_sample_dly× Tspi_ref_clk) — — ns
Figure 7. SPI Master Output Timing Diagram
Figure 8. SPI Master Input Timing Diagram
Table 85.  SPI Slave Timing Requirements for Intel® Stratix® 10 Devices
Symbol Description Min Typ Max Unit
Tspi_ref_clk The period of the SPI internal reference clock, sourced from l4_main_clk 2.5 — — ns
Tclk SPIM_CLK clock period 30 — — ns
Tdutycycle SPIM_CLK duty cycle 45 50 55 %
Td Master-in slave-out (MISO) output skew (2 × Tspi_ref_clk) + 3 — (3 × Tspi_ref_clk) + 11 ns
Tsu Master-out slave-in (MOSI) setup time 4 — — ns
Th Master-out slave-in (MOSI) hold time 9 — — ns
Tsuss SPI_SS_N asserted to first SPIM_CLK edge Tspi_ref_clk + 4 — — ns
Thss Last SPIM_CLK edge to SPI_SS_N deasserted Tspi_ref_clk + 4 — — ns
Figure 9. SPI Slave Output Timing Diagram
Figure 10. SPI Slave Input Timing Diagram
Related Information
140 SPI_SS_N behavior differs depending on Motorola SPI, TI SSP or Microwire operational mode.
141 The capture edge differs depending on the operational mode. For Motorola SPI, the capture edge can be the rising or falling edge depending on the scpol register bit; for TI SSP, the capture edge is the falling edge; for Microwire, the capture edge is the rising edge.
142 Valid values of rx_sample_dly range from 1 to 64 (units are in T spi_ref_clk steps).
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