Intel® Stratix® 10 Device Datasheet

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ID 683181
Date 12/08/2023
Public
Document Table of Contents
Document Table of Contents x
Intel® Stratix® 10 Device Datasheet
Intel® Stratix® 10 Device Datasheet x
Electrical Characteristics Switching Characteristics Configuration Specifications I/O Timing Programmable IOE Delay Glossary Document Revision History for the Intel® Stratix® 10 Device Datasheet
Electrical Characteristics x
Operating Conditions
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot and Undershoot Voltage Recommended Operating Conditions DC Characteristics I/O Standard Specifications
Recommended Operating Conditions x
Recommended Operating Conditions Transceiver Power Supply Operating Conditions HPS Power Supply Operating Conditions
DC Characteristics x
Supply Current and Power Consumption I/O Pin Leakage Current Bus Hold Specifications OCT Calibration Accuracy Specifications OCT Without Calibration Resistance Tolerance Specifications Pin Capacitance Internal Weak Pull-Up Resistor
I/O Standard Specifications x
Single-Ended I/O Standards Specifications Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications Differential SSTL I/O Standards Specifications Differential HSTL and HSUL I/O Standards Specifications Differential I/O Standards Specifications
Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications x
Differential POD12 Standards Specifications
Switching Characteristics x
Core Performance Specifications Periphery Performance Specifications L-Tile Transceiver Performance Specifications H-Tile Transceiver Performance Specifications E-Tile Transceiver Performance Specifications P-Tile Transceiver Performance Specifications HPS Performance Specifications
Core Performance Specifications x
Clock Tree Specifications PLL Specifications DSP Block Specifications Memory Block Specifications Direct Interface Bus (DIB) Specifications Internal Temperature Sensing Diode Specifications External Temperature Sensing Diode Specifications Internal Voltage Sensor Specifications
PLL Specifications x
Fractional PLL Specifications I/O PLL Specifications
Periphery Performance Specifications x
High-Speed I/O Specifications DPA Lock Time Specifications LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specifications Memory Standards Supported by the Hard Memory Controller Memory Standards Supported by the Soft Memory Controller Memory Standards Supported by the HPS Hard Memory Controller DLL Range Specifications Memory Output Clock Jitter Specifications Performance Specifications of the HBM2 Interface in Intel® Stratix® 10 MX, NX, and DX 2100 Devices HBM2 Interface Performance OCT Calibration Block Specifications
L-Tile Transceiver Performance Specifications x
Transceiver Performance for Intel® Stratix® 10 L-Tile Devices Transceiver Specifications for Intel® Stratix® 10 L-Tile Devices
H-Tile Transceiver Performance Specifications x
Transceiver Performance for Intel® Stratix® 10 H-Tile Devices Transceiver Specifications for Intel® Stratix® 10 H-Tile Devices
E-Tile Transceiver Performance Specifications x
Transceiver Performance for Intel® Stratix® 10 E-Tile Devices Transceiver Reference Clock Specifications Transmitter Specifications for Intel® Stratix® 10 E-Tile Devices Receiver Specifications for Intel® Stratix® 10 E-Tile Devices
P-Tile Transceiver Performance Specifications x
Transceiver Performance for Intel® Stratix® 10 DX P-Tile Devices Transceiver Reference Clock Specifications Transmitter Specification for Intel® Stratix® 10 DX P-Tile Devices Receiver Specifications for Intel® Stratix® 10 DX P-Tile Devices
HPS Performance Specifications x
HPS Clock Performance HPS Internal Oscillator Frequency HPS PLL Specifications HPS Cold Reset HPS SPI Timing Characteristics HPS SD/MMC Timing Characteristics HPS USB UPLI Timing Characteristics HPS Ethernet Media Access Controller (EMAC) Timing Characteristics HPS I2C Timing Characteristics HPS NAND Timing Characteristics HPS Trace Timing Characteristics HPS GPIO Interface HPS JTAG Timing Characteristics HPS Programmable I/O Timing Characteristics
HPS PLL Specifications x
HPS PLL Input Requirements HPS PLL Performance
Configuration Specifications x
General Configuration Timing Specifications POR Specifications External Configuration Clock Source Requirements JTAG Configuration Timing AS Configuration Timing Avalon® -ST Configuration Timing Configuration Bit Stream Sizes
Intel® Stratix® 10 Device Datasheet

Transceiver Power Supply Operating Conditions

Table 8.  Transceiver Power Supply Operating Conditions for Intel® Stratix® 10 L-Tile Devices in a Non-Bonded Configuration
Symbol Description Datarate Minimum Typical Maximum Unit
VCCT_GXB[L,R] and VCCR_GXB[L,R] Chip-to-chip 20 1.0 Gbps to 26.6 Gbps 21 22 1.1 1.12 1.14 V
1.0 Gbps to 17.4 Gbps 21 22 1.0 1.03 23 1.06 V
Backplane 24 1.0 Gbps to 12.5 Gbps 21 1.0 1.03 25, 23 1.06 V
VCCH_GXB[L,R] Transceiver high voltage power — 1.71 26 1.8 1.89 V
Table 9.  Transceiver Power Supply Operating Conditions for Intel® Stratix® 10 L-Tile Devices in a Bonded Configuration
Symbol Description Datarate Minimum Typical Maximum Unit
VCCT_GXB[L,R] and VCCR_GXB[L,R] Chip-to-chip 20 1.0 Gbps to 16.0 Gbps 21 1.0 1.03 23 1.06 V
> 16.0 Gbps to 17.4 Gbps 21 22 1.1 1.12 1.14 V
Backplane 24 1.0 Gbps to 12.5 Gbps 21 1.0 1.03 25, 23 1.06 V
VCCH_GXB[L,R] Transceiver high voltage power — 1.71 26 1.8 1.89 V
Table 10.  Transceiver Power Supply Operating Conditions for Intel® Stratix® 10 H-Tile Devices in a Non-Bonded Configuration
Symbol Description Datarate Minimum Typical Maximum Unit
VCCT_GXB[L,R] and VCCR_GXB[L,R] Chip-to-chip 20and Backplane 24 1.0 Gbps to 28.3 Gbps (GXT) 21 1.1 1.12 1.14 V
1.0 Gbps to 17.4 Gbps (GX) 21 1.0 1.03 23 1.06 V
VCCH_GXB[L,R] Transceiver high voltage power — 1.71 26 1.8 1.89 V
Table 11.  Transceiver Power Supply Operating Conditions for Intel® Stratix® 10 H-Tile Devices in a Bonded Configuration
Symbol Description Datarate Minimum Typical Maximum Unit
VCCT_GXB[L,R] and VCCR_GXB[L,R] Chip-to-chip 20 and Backplane 24 1.0 Gbps to 16.0 Gbps 21 1.0 1.03 23 1.06 V
> 16.0 Gbps to 17.4 Gbps 21 1.1 1.12 1.14 V
VCCH_GXB[L,R] Transceiver high voltage power — 1.71 26 1.8 1.89 V
Note: Most VCCR_GXB and VCCT_GXB pins associated with unused transceiver channels can be grounded on a per-tile basis to minimize power consumption. Refer to the Intel® Stratix® 10 Device Family Pin Connection Guidelines and the Intel® Quartus® Prime pin report for information about pinning out the package to minimize power consumption for your specific design.
Table 12.  Transceiver Power Supply Operating Conditions for Intel® Stratix® 10 E-Tile Devices
Symbol Description Minimum 27 Typical Maximum 27 Unit Noise Mask (at ball grid array (BGA))
VCCRT_GXE 28 Transceiver power supply 0.87 0.9 0.93 V

20 mVpp (100 kHz to 400 kHz)

3 mVpp (3 MHz to 500 MHz)

10 mVpp at 1 GHz
VCCRTPLL_GXE 28 Transceiver PLL power supply 0.87 0.9 0.93 V

6 mVpp at 100 kHz

1 mVpp (600 kHz to 10 MHz)

10 mVpp at 1 GHz
VCCH_GXE Analog power supply 1.067 1.1 1.133 V 10 mVpp (800 kHz to 500 MHz
VCCCLK_GXE LVPECL REFCLK power supply 2.375 2.5 2.625 V —
Table 13.  Transceiver Power Supply Operating Conditions for Intel® Stratix® 10 DX P-Tile Devices The specifications below should be met at the board level via direct connection to the package power balls. Place the voltage rail (VR) sense point in the FPGA pinfield as close as possible to the corresponding package power balls. For these rails, measure the output voltage at this remote sense location.
Symbol Description Data Rate Minimum Typical Maximum Unit
VCCRT_GXP 29 Transceiver power supply Up to 16 Gbps 30 0.87 0.90 0.93 V
VCCFUSE_GXP 29 P-tile eFuse power supply 0.87 0.90 0.93 V
VCCCLK_GXP 31 32 P-tile I/O buffer power supply 1.75 1.80 1.85 V
VCCH_GXP 31 32 High voltage power for Transceiver 1.75 1.80 1.85 V
Related Information
20 Chip-to-chip refers to transceiver links that are short reach and do not require advanced equalization such as decision feedback equalization (DFE).
21 Stratix 10 transceivers can support data rates below 1.0 Gbps through over sampling.
22 Bonded channels operating at datarates above 16.0 Gbps require 1.12 V ±20 mV at the pin. For channels that are placed on the same tile as the channels that require 1.12 V ±20 mV, VCCR_GXB and VCCT_GXB = 1.12 V ±20 mV.
23 For a 1.03-V typical voltage, the maximum/minimum should be ± 30 mV; hence, VMAX = 1.06 V. However, when these channels share the power supply with channels requiring a 1.12-V typical voltage, these channels should increase typical voltage to 1.12 V, with a maximum/minimum ± 20 mV; hence VMAX = 1.14 V.
24 Backplane applications refer to ones which require advanced equalization, such as DFE enabled, to compensate for channel loss.
25 Refer to the Intel® Quartus® Prime Pro Edition software for the typical nominal value.
26 In an optical transfer network (OTN) application, the minimum VCCH voltage specification at the package pin is 1.77 V.
27 This value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the PDN tool for the additional budget for the dynamic tolerance requirements.
28 The difference between VCCRT/VCCRTPLL and VCCH should be no less than 200 mV.
29 The recommended DC setpoint is 0.5% of the typical value, the recommended VR ripple and AC transient sum up to 2.5% of the typical value.
30 The data rate includes Intel® PCIe* Gen1 through Gen4 protocols and Intel® UPI protocol at 9.6 Gbps and 10.4 Gbps.
31 The recommended DC setpoint is 0.5% of the typical value, the recommended VR ripple is 0.5% of the typical value, and the recommended AC transient is 2% of the typical value.
32 Follow the more stringent tolerance range for the voltage rails connecting multiple power supplies.
Level Two Title