PCB Stackup Design Considerations for Intel® FPGAs

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ID 683883
Date 6/28/2017
Public
Document Table of Contents
Document Table of Contents x
1. PCB Stackup Design Considerations for Intel® FPGAs
1. PCB Stackup Design Considerations for Intel® FPGAs x
1.1. PCB Stackup Construction 1.2. Material Selection 1.3. Glass Transition Temperature 1.4. PCB Stackup Design 1.5. PCB Panelization 1.6. Conclusion 1.7. Specific Recommendations for Intel® FPGA Devices 1.8. References 1.9. Document Revision History
1.2. Material Selection x
1.2.1. Material Loss Considerations
1.2.1. Material Loss Considerations x
1.2.1.1. Relative Dielectric Constant 1.2.1.2. Loss Tangent 1.2.1.3. Fiberglass Weave Composition 1.2.1.4. Skin Effect
1.4. PCB Stackup Design x
1.4.1. Layer Count 1.4.2. Signal Layers 1.4.3. High Speed Signal Layer Planning 1.4.4. Power and Ground Layers 1.4.5. Power Plane and Capacitor Placement Strategy 1.4.6. Planar Capacitance and Spreading Inductance 1.4.7. Plane Layer Separation 1.4.8. Copper Weight 1.4.9. Hybrid Construction
1.4.5. Power Plane and Capacitor Placement Strategy x
1.4.5.1. General Rules for Capacitor and Power Plane Placement 1.4.5.2. Rules for Transceiver Power Plane Placement 1.4.5.3. Rules for High-Current Power Rails 1.4.5.4. Rules for PLL and Other Power Rails
1.7. Specific Recommendations for Intel® FPGA Devices x
1.7.1. Stratix® 10 Device Recommendations 1.7.2. Stratix® V Device Recommendations 1.7.3. Stratix IV Device Recommendations 1.7.4. Arria® 10 Device Recommendations 1.7.5. Arria® V Device Recommendations 1.7.6. Arria II Device Recommendations 1.7.7. Cyclone® 10 Device Recommendations 1.7.8. Cyclone® V Device Recommendations 1.7.9. Cyclone® IV Device Recommendations 1.7.10. Cyclone III Device Recommendations
1.7.1. Stratix® 10 Device Recommendations x
1.7.1.1. Stratix® 10 Device Family Power Plane Placement Example
1.7.2. Stratix® V Device Recommendations x
1.7.2.1. Stratix® V GX, GT, and GS Family Power Plane Placement Example 1.7.2.2. Stratix® V E Family Power Plane Placement Example 1.7.2.3. Stratix® V Transceiver Channel Breakout Recommendations
1.7.3. Stratix IV Device Recommendations x
1.7.3.1. Stratix IV GX and GT Family Power Plane Placement Example 1.7.3.2. Stratix IV E Family Power Plane Placement Example
1.7.4. Arria® 10 Device Recommendations x
1.7.4.1. Arria® 10 Device Family Power Plane Placement Example
1.7.5. Arria® V Device Recommendations x
1.7.5.1. Arria® V Device Family Power Plane Placement Example
1.7.6. Arria II Device Recommendations x
1.7.6.1. Arria II GX Family Power Plane Placement Example
1.7.7. Cyclone® 10 Device Recommendations x
1.7.7.1. Cyclone® 10 LP Device Family Power Plane Placement Example
1.7.8. Cyclone® V Device Recommendations x
1.7.8.1. Cyclone® V Device Family Power Plane Placement Example
1.7.9. Cyclone® IV Device Recommendations x
1.7.9.1. Cyclone® IV GX Family Power Plane Placement Example 1.7.9.2. Cyclone® IV E Family Power Plane Placement Example
1.7.10. Cyclone III Device Recommendations x
1.7.10.1. Cyclone III Family Power Plane Placement Example
1. PCB Stackup Design Considerations for Intel® FPGAs

1.5. PCB Panelization

Always consider board panelization during the initial PCB sizing to maximize the number of board yield per PCB panel and reduce the cost per board. Although common PCB panel dimensions are 12 × 18 in and 18 × 24 in, the actual usable area left to the designer is typically one inch less on all sides of the panel. Therefore, the usable dimensions are 10 × 16 in and 16 × 22 in, respectively. Also, when panelizing multiple boards up on a PCB panel, the minimum spacing requirement between boards must be 100 mils to allow the individual boards to be routed out after fabrication. Below figure shows an example of maximum panel utilization on an 18 × 24 in panel. In this example, six Stratix IV GX SI development kit boards have been panelized as 6-up on a standard 18 × 24 in panel with 100 mil separation between adjacent boards to accommodate final routing of the board.
Figure 16. PCB Panelization
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