PCB Stackup Design Considerations for Intel® FPGAs

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ID 683883
Date 6/28/2017
Public
Document Table of Contents
Document Table of Contents x
1. PCB Stackup Design Considerations for Intel® FPGAs
1. PCB Stackup Design Considerations for Intel® FPGAs x
1.1. PCB Stackup Construction 1.2. Material Selection 1.3. Glass Transition Temperature 1.4. PCB Stackup Design 1.5. PCB Panelization 1.6. Conclusion 1.7. Specific Recommendations for Intel® FPGA Devices 1.8. References 1.9. Document Revision History
1.2. Material Selection x
1.2.1. Material Loss Considerations
1.2.1. Material Loss Considerations x
1.2.1.1. Relative Dielectric Constant 1.2.1.2. Loss Tangent 1.2.1.3. Fiberglass Weave Composition 1.2.1.4. Skin Effect
1.4. PCB Stackup Design x
1.4.1. Layer Count 1.4.2. Signal Layers 1.4.3. High Speed Signal Layer Planning 1.4.4. Power and Ground Layers 1.4.5. Power Plane and Capacitor Placement Strategy 1.4.6. Planar Capacitance and Spreading Inductance 1.4.7. Plane Layer Separation 1.4.8. Copper Weight 1.4.9. Hybrid Construction
1.4.5. Power Plane and Capacitor Placement Strategy x
1.4.5.1. General Rules for Capacitor and Power Plane Placement 1.4.5.2. Rules for Transceiver Power Plane Placement 1.4.5.3. Rules for High-Current Power Rails 1.4.5.4. Rules for PLL and Other Power Rails
1.7. Specific Recommendations for Intel® FPGA Devices x
1.7.1. Stratix® 10 Device Recommendations 1.7.2. Stratix® V Device Recommendations 1.7.3. Stratix IV Device Recommendations 1.7.4. Arria® 10 Device Recommendations 1.7.5. Arria® V Device Recommendations 1.7.6. Arria II Device Recommendations 1.7.7. Cyclone® 10 Device Recommendations 1.7.8. Cyclone® V Device Recommendations 1.7.9. Cyclone® IV Device Recommendations 1.7.10. Cyclone III Device Recommendations
1.7.1. Stratix® 10 Device Recommendations x
1.7.1.1. Stratix® 10 Device Family Power Plane Placement Example
1.7.2. Stratix® V Device Recommendations x
1.7.2.1. Stratix® V GX, GT, and GS Family Power Plane Placement Example 1.7.2.2. Stratix® V E Family Power Plane Placement Example 1.7.2.3. Stratix® V Transceiver Channel Breakout Recommendations
1.7.3. Stratix IV Device Recommendations x
1.7.3.1. Stratix IV GX and GT Family Power Plane Placement Example 1.7.3.2. Stratix IV E Family Power Plane Placement Example
1.7.4. Arria® 10 Device Recommendations x
1.7.4.1. Arria® 10 Device Family Power Plane Placement Example
1.7.5. Arria® V Device Recommendations x
1.7.5.1. Arria® V Device Family Power Plane Placement Example
1.7.6. Arria II Device Recommendations x
1.7.6.1. Arria II GX Family Power Plane Placement Example
1.7.7. Cyclone® 10 Device Recommendations x
1.7.7.1. Cyclone® 10 LP Device Family Power Plane Placement Example
1.7.8. Cyclone® V Device Recommendations x
1.7.8.1. Cyclone® V Device Family Power Plane Placement Example
1.7.9. Cyclone® IV Device Recommendations x
1.7.9.1. Cyclone® IV GX Family Power Plane Placement Example 1.7.9.2. Cyclone® IV E Family Power Plane Placement Example
1.7.10. Cyclone III Device Recommendations x
1.7.10.1. Cyclone III Family Power Plane Placement Example
1. PCB Stackup Design Considerations for Intel® FPGAs

1.2.1.3. Fiberglass Weave Composition

The fiberglass within the core and prepreg is constructed by weaving fibers of glass yarn together to form fabric-like fiberglass sheets. These sheets are then impregnated with an epoxy resin to form the core (cured resin) and prepreg (uncured resin) materials. Because the glass yarn comes in different densities and thicknesses, the resulting sheets can range from loosely-weaved to tightly-weaved fiberglass-epoxy fill.

Figure 3. Different Styles of Fibreglss Weaves

The fiberglass weaves are typically classified into different glass styles, based on the yarn count and the type of fiberglass yarn used, as listed in below table.

Table 3.  Common Fibreglass Weave Styles
Glass Style Count Warp Count per Inch Warp Yarn Yarn Fill Glass Thickness
106 56 56 ECD-900 1/0 ECD-900 1/0 0.0015
1080 60 47 ECD-450 1/0 ECD-450 1/0 0.0025
1280 60 60 ECD-450 1/0 ECD-450 1/0 0.0022
2113 60 56 ECE-225 1/0 ECD-450 1/0 0.0029
2116 60 58 ECE-225 1/0 ECE-225 1/0 0.0038
3070 70 70 ECDE-300 1/0 ECDE-300 1/0 0.0034
1652 52 52 ECG-150 1/0 ECG-150 1/0 0.0045
7628 44 31 ECG-75 1/0 ECG-75 1/0 0.0068

The tighter the weave netting, the more uniform the dielectric constant. Loose weaves resulting in less uniform dielectric constants in the PCB laminate can cause trace impedance variations and propagation skews in tightly matched signals, such as differential pairs that directly reference the weave. For example, on a sparse weaving such as glass style 106, one leg of the differential pair may be routed directly over a fiber weave while the other leg is routed between the fiber weaves. This results in a different εr for each leg of the differential channel.

In general, to counteract this skew, route traces at a small angle in a zig-zag fashion relative to the fiberglass strands to average out the number of on-weave and off-weave traces. This technique requires more board routing room and may not be achievable in a space-constrained board. In this situation, select a more tightly woven glass style for the dielectric surrounding the high speed trace layers. Because more tightly woven glass styles add cost to the PCB, a good compromise is to select a medium woven glass style such as 2116 for the high-speed trace layers and a lower-cost 106 or 1080 glass style for other lower-speed signal layers.

For board design with ultra-high speed transceiver signals, Intel® recommends to choose spread glass materials to mitigate this effect.

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