3.3.1.1. Modifying Stratix® V Design Examples

Intel® Quartus® Prime Standard Edition User Guide: Debug Tools

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ID 683552

Date 9/24/2018

Version 18.1

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3.3.1.1. Modifying Stratix® V Design Examples

You can adapt Intel FPGA design examples to experiment with configurations that match your own design. For example, you can change data rate, number of lanes, PCS-PMA width, FPGA-fabric interface width, or input reference clock frequency. To modify the design examples, change the IP core parameters and regenerate the system in Platform Designer (Standard). Next, update the top-level design file, and re-assign device I/O pins as necessary.

To modify a Stratix® V design example PHY block to match your design, follow these steps:

Determine the number of channels your design requires.
Open the <project name> .qpf for the design example in the Intel® Quartus® Prime software.
Click Tools > Platform Designer (Standard) .
On the System Contents tab, right-click the PHY block and click Edit. Specify options for the PHY block to match your design requirement for number of lanes, data rate, PCS-PMA width, FPGA-fabric interface width, and input reference clock frequency.
Specify a multiple of the FPGA-fabric interface data width for Avalon® Data Symbol Size. The available values are 8 or 10. Click Finish.
Delete any timing adapter from the design. The timing adapters are not required.
From the IP Catalog, add one Data Pattern Generator and Data Pattern Checker for each transmitter and receiver lane.
Right-click Data Pattern Generator and click Edit. Specify a value for ST_DATA_W that matches the FPGA-fabric interface width.
Right-click Data Pattern Checker and click Edit. Specify a value for ST_DATA_W that matches the FPGA-fabric interface width.
From the IP Catalog, add a Transceiver Reconfiguration Controller.
Right-click Transceiver Reconfiguration Controller and click Edit. Specify 2* number of lanes for the number of reconfigurations interfaces. Click finish.

Create connections for the data pattern generator and data pattern checker components. Right-click the net name in the System Contents tab and specify the following connections.

From		To
Block Name	Net Name	Block Name	Net Name
`clk_100`	`clk`	`data_pattern_generator`	`csr_clk`
`clk_100`	`clk_reset`	`data_pattern_generator`	`csr_clk_reset`
`master_0`	`master`	`data_pattern_generator`	`csr_slave`
`xcvr_*_phy_0`	`tx_clk_out0`	`data_pattern_generator`	`pattern_out_clk`
`xcvr_*_phy_0`	`tx_parallel_data0`	`data_pattern_generator`	`pattern_out`
`clk_100`	`clk`	`data_pattern_checker`	`csr_clk`
`clk_100`	`clk_reset`	`data_pattern_checker`	`csr_clk_reset`
`master_0`	`master`	`data_pattern_checker`	`csr_slave`
`xcvr_*_phy_0`	`rx_clk_out0`	`data_pattern_checker`	`pattern_in_clk`
`xcvr_*_phy_0`	`rx_parallel_data0`	`data_pattern_checker`	`pattern_in`

Click System > Assign Base Addresses.
Connect the reset port of timing adapters to clk_reset of clk_100.
To implement the changes to the system, click Generate > Generate HDL.
If you modify the number of lanes in the PHY, you must update the top-level file accordingly. The following example shows Verilog HDL code for a two-channel design that declares input and output ports in the top-level design. The example design includes the low latency PHY IP core. If you modify the PHY parameters, you must modify the top-level design with the correct port names. Platform Designer (Standard) displays an example of the PHY, click Generate > HDL Example.
```
module low_latency_10g_1ch DUT ( 
						input  wire GXB_RXL11,
						input  wire GXB_RXL12,
						output wire GXB_TXL11,
						output wire GXB_TX12
						);
						.....
						low_latency_10g_1ch DUT (
						.....
						.xcvr_low_latency_phy_0_tx_serial_data_export	({GXB_TXL11, 	GXB_TXL12}),		
						.xcvr_low_latency_phy_0_rx_serial_data_export	({GXB_RXL11, 		GXB_TXL12}),		
						.....
						);
```
From the Intel® Quartus® Prime software, click Assignments > Pin Planner and update pin assignments to match your board.
Edit the design’s Synopsys Design Constraints (.sdc) to reflect the reference clock change. Ignore the reset warning messages.
Click Start > Start Compilation to recompile the design.

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Intel® Quartus® Prime Standard Edition User Guide: Debug Tools

3.3.1.1. Modifying Stratix® V Design Examples