Avalon Verification IP Suite: User Guide

ID 683439
Date 2/17/2022
Public
Document Table of Contents

6.1. Timing

The following timing diagram illustrates the sequence of events for an Avalon-MM Slave BFM. It shows the slave BFM responding to interleaved writes and reads when the readdatavalid signal is present.
Figure 8. Avalon-MM Slave Responding to Interleaved Write and Read Transactions
Table 8.  Key to AnnotationsThe following table lists the annotations used in this figure.
Symbol Description
Twt_1 The response wait time, which is three cycles. The slave sets this value using the set_interface_wait_time command.
Twr waitrequest is sampled #1 after the falling edge of clk.
Twt_2 The response wait time for the first read, which is 2 cycles. The slave sets this value using the set_interface_wait_time command.
Scr_1–Scr_2 Signals when read commands were received. The event name is signal_command_received.
Trl_1,Trl_2 The response latency for the reads, which is 3 cycles. The slave sets this time using the set_response_latency command.
Twrl_1 The write response latency for the first write, which is 3 cycles. This is the time between when the write command is accepted, and the write response is provided by the slave. T
Src_1,Src_3 Signals write responses. The event name is signal_response_issued.
Src_2,Src_4 Signals read responses. The event name is signal_response_issued.
TID_1–TID_4 Reference number to identify each read or write transaction.
ID_1, ID_3 Reference number to identify write transactions.
ID_2, ID_4 Reference number to identify read transactions.
Figure 9. Avalon-MM Slave Receiving Write and Read Commands with No readdatavalid SignalThe following timing diagram illustrates the sequence of events for an Avalon-MM Slave BFM. The slave BFM receives a write followed by a read when the readdatavalid signal is not present.
Table 9.  Key to AnnotationsThe following table lists the annotations used in this figure.
Symbol Description
Ti The initial command latency which is two cycles for transactions 1 and 2.
Twt_1 The response wait time which is 3 cycles. The master gets this value using the get_response_wait_time command.
Twt_2 The response wait time for the first read, which is 2 cycles. The slave sets this value using the set_interface_wait_time command.
Twr waitrequest is sampled #1 after the falling edge of clk.
Trl_1 The response latency for the first read, which is 0 cycles. The master gets this time using the get_response_latency command.
Scr_1, Scr_2 Signals write and read commands. The event name is signal_command_issued.
Src_1 Signals the first read response. The event name is signal_response_complete.
Satc Signals the end of the test. The event name is signal_all_transactions_complete