Avalon Verification IP Suite: User Guide

ID 683439
Date 2/17/2022
Public
Document Table of Contents

10.2.7.26. set_enable_c_valid_non_ready()

Prototype:

set_enable_c_valid_non_ready()

Arguments:

Verilog HDL: Boolean

VHDL: N.A.

Returns:

void

Description:

Enables a coverage point that ensures test coverage for valid signal when ready is deasserted. It is disabled when the readyLatency is greater than 0.
Language support: Verilog HDL