FIR II IP Core: User Guide

ID 683208
Date 8/14/2023
Public

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4.4.3.2. Four Channels on Four Wires

Figure 21. Four Channels on Four Wires (Input)
Figure 22. Four Channels on Four Wires (Output)

This result appears to be vertical, but that is because the number of cycles is 1, so on each wire there is only space for one piece of data.

Figure 23. Four Channels on Four Wires with Double Clock Rate (Input)
Figure 24. Four Channels on Four Wires with Double Clock Rate (Output)