FIR II IP Core: User Guide

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ID 683208
Date 8/14/2023
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Document Table of Contents
Document Table of Contents x
1. About the FIR II IP Core 2. FIR II IP Core Getting Started 3. FIR II IP Core Parameters 4. FIR II IP Core Functional Description 5. Document Revision History for the FIR II IP User Guide A. FIR II IP Core Document Archive
1. About the FIR II IP Core x
1.1. DSP Intel® FPGA IP Features 1.2. FIR II IP Core Features 1.3. FIR II IP Device Support 1.4. DSP Intel® FPGA IP Verification 1.5. FIR II IP Core Release Information 1.6. FIR II IP Core Performance and Resource Utilization
2. FIR II IP Core Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. IP Catalog and Parameter Editor 2.3. Specifying the IP Core Parameters and Options ( Intel® Quartus® Prime Pro Edition) 2.4. Simulating Intel® FPGA IP Cores 2.5. Simulating the FIR II IP Core Testbench in MATLAB 2.6. DSP Builder for Intel® FPGAs Design Flow
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode 2.1.2. FIR II IP Core Intel® FPGA IP Evaluation Mode Timeout Behavior
2.3. Specifying the IP Core Parameters and Options ( Intel® Quartus® Prime Pro Edition) x
2.3.1. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition)
3. FIR II IP Core Parameters x
3.1. FIR II IP Core Filter Specification 3.2. FIR II IP Core Coefficient Settings 3.3. FIR II IP Core Coefficients 3.4. FIR II IP Core Input and Output Options 3.5. FIR II IP Core Implementation Options 3.6. FIR II IP Core Reconfigurability
3.3. FIR II IP Core Coefficients x
3.3.1. Loading Coefficients from a File
3.4. FIR II IP Core Input and Output Options x
3.4.1. Signed Fractional Binary 3.4.2. MSB and LSB Truncation, Saturation, and Rounding
3.5. FIR II IP Core Implementation Options x
3.5.1. Memory and Multiplier Trade-Offs
3.5.1. Memory and Multiplier Trade-Offs x
3.5.1.1. Using Memory Block Threshold 3.5.1.2. Using Dual-port RAM Threshold 3.5.1.3. Using Large RAM Threshold 3.5.1.4. Using Hard Multiplier Threshold
4. FIR II IP Core Functional Description x
4.1. FIR II IP Core Interpolation Filters 4.2. FIR Decimation Filters 4.3. FIR II IP Core Time-Division Multiplexing 4.4. FIR II IP Core Multichannel Operation 4.5. FIR II IP Core Multiple Coefficient Banks 4.6. FIR II IP Core Coefficient Reloading 4.7. Reconfigurable FIR Filters 4.8. FIR II IP Core Interfaces and Signals
4.4. FIR II IP Core Multichannel Operation x
4.4.1. Vectorized Inputs 4.4.2. Channelization 4.4.3. Channel Input and Output Format
4.4.3. Channel Input and Output Format x
4.4.3.1. Eight Channels on Three Wires 4.4.3.2. Four Channels on Four Wires 4.4.3.3. 15 Channels with 15 Valid Cycles and 17 Invalid Cycles 4.4.3.4. 22 Channels with 11 Valid Cycles and 9 Invalid Cycles 4.4.3.5. Super Sample Rate
4.8. FIR II IP Core Interfaces and Signals x
4.8.1. Avalon Streaming Interfaces in DSP Intel FPGA IP 4.8.2. FIR II IP Core Avalon-ST Interfaces 4.8.3. FIR II IP Core Signals
4.8.2. FIR II IP Core Avalon-ST Interfaces x
4.8.2.1. Avalon-ST Sink Interface 4.8.2.2. Avalon-ST Source Interface
4.8.2.1. Avalon-ST Sink Interface x
4.8.2.1.1. Single Channel on Single Wire 4.8.2.1.2. Multiple Channels on Single Wire 4.8.2.1.3. Multiple Channels on Multiple Wires
1. About the FIR II IP Core
2. FIR II IP Core Getting Started
3. FIR II IP Core Parameters
4. FIR II IP Core Functional Description
5. Document Revision History for the FIR II IP User Guide
A. FIR II IP Core Document Archive

3.1. FIR II IP Core Filter Specification

Table 8.  Filter Specification Parameters
Parameter Value Description
Filter Settings
Filter Type Single Rate

Decimation

Interpolation

Fractional Rate

The type of FIR filter.
Interpolation Factor 1 to 128 The number of extra points to generate between the original samples.
Decimation Factor 1 to 128 The number of data points to remove between the original samples.
Maximum Number of Channels 1–128 The number of unique input channels to process.
Frequency Specification
Clock Frequency (MHz) 1–500 The frequency of the input clock.
Clock Slack Integer The amount of pipelining you can control independently of the clock frequency and therefore independently of the clock to sample rate ratio.
Input Sample Rate (MSPS) Real The sample rate of the incoming data.
Coefficient Options
Coefficient Scaling Auto

None

 The coefficient scaling mode. Select Auto to apply a scaling factor in which the maximum coefficient value equals the maximum possible value for a given number of bits. Select None to read in pre-scaled integer values for the coefficients and disable scaling.
Coefficient Data Type Signed Binary

Signed Fractional Binary

The coefficient input data type. Select Signed Fractional Binary to monitor which bits are preserved and which bits are removed during the filtering process.
Coefficient Bit Width 2–32 The width of the coefficients. The default value is 8 bits.
Coefficient Fractional Bit Width 0–32 The width of the coefficient data input into the filter when you select Signed Fractional Binary as your coefficient data type.
Coefficients Reload Options
Coefficients Reload — Turn on this option to allow coefficient reloading, which allows you to change coefficient values during run time. Also, additional input ports are added to the filter.
Base Address Integer The base address of the memory-mapped coefficients.
Read/Write mode Read

Write

Read/Write

The read and write mode that determines the type of address decode to build.
Flow Control
Back Pressure Support — Turn on for backpressure support. When you turn on this option, the sink indicates to the source to stop the flow of data when its FIFO buffers are full or when there is congestion on its output port.
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