FIR II IP Core: User Guide

ID 683208
Date 8/14/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.8.2.2. Avalon-ST Source Interface

The source interface can handle single or multiple channels on a single wire and multiple channels on multiple wires. The IP core includes an Avalon-ST FIFO in the source wrapper when the backpressure support is turned on. The Avalon-ST FIFO controls the backpressure mechanism and catches the extra cycles of data from the FIR II IP core after backpressure. On the input side of the FIR II IP core, driving the enable_i signal low, causes the FIR II IP core to stop. From the output side, backpressure drives the enable_i signal of the FIR II IP core. If the downstream module can accept data again, the FIR II IP core is instantly re-enabled.

When the packet size is greater than one (multichannel), the source interface expects your application to supply the count of data starting from 1 to the packet size. When the source interface receives the valid flag together with the data_count = 1, it starts sending out data by driving both the ast_source_sop and ast_source_valid signals high. When data_count equals the packet size, the ast_source_eop signal is driven high together with the ast_source_valid signal.

If the downstream components are not ready to accept any data, the source interface drives the source_stall signal high to tell the design to stall.

Figure 43. Multiple Channels on Multiple Wires The FIR II IP core to the source interface when transferring a packet of data over multiple channels on multiple wires.
Figure 44. Timing Diagram of Multiple Channels on Multiple WiresThe FIR II IP core to the source interface when transferring a packet of data over multiple channels on multiple wires.