MAX® 10 FPGA Design Guidelines

ID 683196
Date 5/15/2024
Public
Document Table of Contents

1.6.2.8. Verify the usage of the VREF pins that are used as regular I/Os

VREF pins have higher pin capacitance that results in a different I/O timing:
  • Do not use these pins in a grouped interface such as a bus.
  • Do not use these pins for high edge rate signals such as clocks.