MAX® 10 FPGA Design Guidelines

ID 683196
Date 5/15/2024
Public
Document Table of Contents

1.8.1.1. Specify your synthesis tool and use correct supported version

The Quartus® Prime software includes integrated synthesis that fully supports Verilog HDL, VHDL, Altera hardware description language (AHDL), and schematic design entry. You can also use industry-leading third-party EDA synthesis tools to synthesize your Verilog HDL or VHDL design, and then compile the resulting output netlist file in the Quartus® Prime software:
  • Specify a third-party synthesis tool in the New Project Wizard or the EDA Tools Settings page of the Settings dialog box to use the correct Library Mapping File (.lmf) for your synthesis netlist.
  • Altera recommends that you use the most recent version of third-party synthesis tools because tool vendors are continuously adding new features, fixing tool issues, and enhancing performance for Altera devices.
  • Different synthesis tools can give different results. If you want to select the best-performing tool for your application, you can experiment by synthesizing typical designs for your application and coding style, and comparing the results.
  • Perform placement and routing in the Quartus® Prime software to get accurate timing analysis and logic utilization results.
  • Your synthesis tool may offer the capability to create a Quartus® Prime project and pass constraints such as the EDA tool setting, device selection, and timing requirements that you specified in your synthesis project. You can use this capability to save time when setting up your Quartus® Prime project for placement and routing.