MAX® 10 FPGA Design Guidelines

ID 683196
Date 5/15/2024
Public
Document Table of Contents

1.7.8. Review recommended reset architecture

  • If the clock signal is not available when reset is asserted, an asynchronous reset is typically used to reset the logic.
  • The recommended reset architecture allows the reset signal to be asserted asynchronously and deasserted synchronously.
  • The source of the reset signal is connected to the asynchronous port of the registers, which can be directly connected to global routing resources.
  • The synchronous deassertion allows all state machines and registers to start at the same time.
  • Synchronous deassertion avoids an asynchronous reset signal from being released at, or near, the active clock edge of a flipflop that can cause the output of the flipflop to go to a metastable unknown state.