MAX® 10 FPGA Design Guidelines

ID 683196
Date 5/15/2024
Public
Document Table of Contents

1.5.1.2. Ensure board support the required features:

  • Data decompression—if you enable data compression, the storage requirement and the programming time (writing to flash) are reduced. The configuration time (writing to CRAM) is increased.
  • Design security—this feature utilizes a 128-bit security key to protect the designs from unauthorized copying, reverse engineering, and tampering. The devices can decrypt configuration bitstreams using the AES algorithm. Design security is not available for the JTAG configuration scheme.
  • Dual configuration—this feature is supported only in self-download mode.
  • SEU mitigation—dedicated circuitry in the devices perform cyclic redundancy check (CRC) error detection and check for SEU errors automatically. To detect SEU errors, use the CRC_ERROR pin to flag errors and design your system to take appropriate action. If you do not enable the CRC error detection feature, you can also use the CRC_ERROR pin as a design I/O pin.