Ethernet Design Example Components User Guide

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ID 683044
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. Time-of-day Clock 2. Time-of-day Synchronizer 3. Packet Classifier 4. Ethernet Design Example Components User Guide Archives 5. Document Revision History for the Ethernet Design Example Components User Guide
1. Time-of-day Clock x
1.1. Release Information 1.2. Resource Utilization 1.3. Configuring the TOD Clock 1.4. Using the TOD Clock 1.5. Interface Signals 1.6. Configuration Registers
1.1. Release Information x
1.1.1. Pulse Per Second Device Speed Grade Support
1.4. Using the TOD Clock x
1.4.1. Adjusting TOD Drift 1.4.2. Adjusting Offset, Jitter, and Wander 1.4.3. Correcting TOD Offset 1.4.4. IOPLL and TOD Setup for Pulse Per Second (Advanced Accuracy Mode)
1.4.4. IOPLL and TOD Setup for Pulse Per Second (Advanced Accuracy Mode) x
1.4.4.1. IOPLL and TOD Setup using Dynamic Phase Shift Interface 1.4.4.2. IOPLL and TOD Setup using IOPLL Reconfig IP
1.5. Interface Signals x
1.5.1. Avalon Memory-Mapped Signals 1.5.2. Time-of-day Signals 1.5.3. Pulse-Per-Second Signals 1.5.4. Clocking Requirements
2. Time-of-day Synchronizer x
2.1. Release Information 2.2. Resource Utilization 2.3. Configuring the TOD Synchronizer 2.4. Using the TOD Synchronizer 2.5. Interface Signals
2.4. Using the TOD Synchronizer x
2.4.1. Sampling Clock Frequency
3. Packet Classifier x
3.1. Release Information 3.2. Resource Utilization 3.3. Configuring the Packet Classifier 3.4. Interface Signals
3.4. Interface Signals x
3.4.1. Clock and Reset Signals 3.4.2. Avalon® Streaming Interface Signals 3.4.3. Control Signals
1. Time-of-day Clock
2. Time-of-day Synchronizer
3. Packet Classifier
4. Ethernet Design Example Components User Guide Archives
5. Document Revision History for the Ethernet Design Example Components User Guide

5. Document Revision History for the Ethernet Design Example Components User Guide

Document Version Quartus® Prime Version Changes
2024.04.01 24.1
  • Added support for Agilex™ 5 devices for Ethernet IEEE 1588 Time of Day Clock Intel® FPGA IP, Ethernet IEEE 1588 TOD Synchronizer Intel® FPGA IP, and Ethernet Packet Classifier Intel® FPGA IP:
    • Updated Supported Device Speed Grades table.
    • Added Estimated Resource Utilization in Intel Agilex 5 Devices (A5EC065BB32AE6S) table.
  • Updated the term "slave" to "target".
2023.11.21 22.3 Updated iopll_scan_clk description in the Pulse Per Second Signals table.
2023.10.02 22.3 Updated the Sampling Clock Frequency topic. Added links to the Agilex™ 7 Clocking and PLL User Guide: F-Series and I-Series and the Stratix® 10 Clocking and PLL User Guide.
2023.08.21 22.3
  • Updated Adjusting Offset, Jitter, and Wander topic.
  • Updated IOPLL and TOD Setup using Dynamic Phase Shift Interface topic.
  • Updated IOPLL and TOD Setup using IOPLL Reconfig IP topic.
  • Updated Example of connection between IOPLL, IOPLL reconfig IP, and TOD's Advanced Accuracy Pulse Per Second Interfaces figure.
  • Updated product family name to " Intel Agilex® 7".
2022.09.27 22.3
  • Updated the following Resource Utilization tables for Time-of-day Clock:
    • Estimated Resource Utilization in Stratix® V Devices (5SGXEA7H3F35C3)
    • Estimated Resource Utilization in Intel® Arria® 10 Devices (10AX115H1F34I1SG)
    • Estimated Resource Utilization in Intel® Stratix® 10 Devices (1SG280HN2F43E1VG)
    • Estimated Resource Utilization in Intel Agilex® Devices (AGFB014R24A2E2V)
  • Updated the following Resource Utilization tables for Time-of-day Synchronizer:
    • Estimated Resource Utilization in Intel® Arria® 10 Devices (10AX115H1F34I1SG)
    • Estimated Resource Utilization in Intel® Stratix® 10 Devices (1SG280HN2F43E1VG)
    • Estimated Resource Utilization in Intel Agilex® Devices (AGFB014R24A2E2V)
  • Updated Pulse Width parameter description in Pulse Per Second Parameter Description table.
2022.03.28 22.1 Added new IOPLL and TOD Setup using IOPLL Reconfig IP topic.
2021.12.13 21.4
  • Edited the following tables:
    • Estimated Resource Utilization in Intel® Stratix® 10 Devices (1SG280LN2F43E1VG)
    • Estimated Resource Utilization in Intel Agilex® Devices (AGFA022R24C212V)
  • Updated Clocking Requirements topic.
  • Updated Supported Speed Grades in Pulse Per Second Device Speed Grade Support topic.
2021.09.27 21.3
  • Added new section Pulse Per Second Device Speed Grade Support in the topic Release Information.
  • Edited Resource Utilization and added Pulse Per Second Configuration to the following tables:
    • Estimated Resource Utilization in Intel® Arria® 10 Devices (10AX115U2F45I2SGES).
    • Estimated Resource Utilization in Intel Agilex® Devices (AGFA014F25AA212V).
  • Added new table: Pulse Per Second Parameter in Configuring the TOD Clock.
  • Added new section IOPLL and TOD Setup for Pulse Per Second (Advanced Accuracy Mode) in Using the TOD Clock.
  • Added new section Pulse-Per-Second Signals in the topic Interface Signals.
  • Edited table: Register Description
    • Changed Byte Offset to Word Offset.
    • Added new row for 0x0B Word Offset.
  • Removed Intel Max 10 as the Supported Devices from table: Ethernet IEEE 1588 TOD Synchronizer Intel® FPGA IP Release Information.
2021.03.29 21.1
  • Added new tables:
    • Sampling Clock Granularity for Sampling Clock Factor
    • Sampling Clock Granularity Using 80 MHz Sampling Clock
2020.12.14 20.4
  • Updated chapter Time-of-day Synchronizer and table TOD Synchronizer Parameters Description to include frequency 402.83 MHz and also its parameters.
  • Added figure TOD Synchronizer in a Design (SYNC_MODE 18) to section Using the TOD Synchronizer.
  • Updated the description for clk_sampling in table Signals Description.
  • Updated the names, values, default values, and descriptions for the following parameters in Table: TOD Clock Parameters Description:
    • Updated parameter name PERIOD_CLOCK_FREQUENCY to Enable high clock frequency mode.
    • Updated parameter name OFFSET_JITTER_WANDER_EN to Enable offset, jitter, and wander supports.
  • Updated the description for AdjustPeriod in Table: Configuration Registers for Time-of-day clock.
2020.07.14 20.2 Updated Adjusting Offset, Jitter, and Wander:
  • Corrected the bits for WanderTimerLSB from [29:1] to [29:0].
  • Corrected the values for WanderTimerMSB[15:0] from 0x06239 to 0x6239.
2020.06.22 20.2
  • Added the following tables in the Time-of-day Clock chapter:
    • Estimated Resource Utilization in Intel® Stratix® 10 Devices (1SG280LN2F43E1VG).
    • Estimated Resource Utilization in Intel Agilex® Devices (AGFA014F25AA212V).
  • Added the following tables in the Time-of-day Synchronizer chapter:
    • Estimated Resource Utilization in Intel® Stratix® 10 Devices (1SX280LN2F43E2LG)
    • Estimated Resource Utilization in Intel Agilex® Devices (AGFB014F25A2E2V)
  • Updated the description for PERIOD_CLOCK_FREQUENCY in Table: TOD Clock Parameters Description.
  • Updated the following topics:
    • Adjusting TOD Drift
    • Adjusting Offset, Jitter, and Wander
    • Correcting TOD Offset
    • Packet Classifier
  • Updated the description for the following registers in Table: Register Description:
    • SecondsH
    • AdjustPeriod
    • AdjustCount
  • Added a new Table: Estimated Resource Utilization in Intel® Stratix® 10 Devices (1SX280LN2F43E2LG).
  • Updated the descriptions to the following signals in Table: Control Signals Description:
    • tx_etstamp_ins_ctrl_in_ingress_timestamp_96b
    • tx_etstamp_ins_ctrl_in_ingress_timestamp_64b
  • Updated for latest Intel branding standards.
2019.09.30 19.3
  • Added support for Intel Agilex® devices in the Time-of-day Clock and Time-of-day Synchronizer chapters.
  • Updated the following tables to include Intel® Quartus® Prime version:
    • Ethernet IEEE 1588 Time of Day Clock Intel® FPGA IP Release Information
    • Ethernet IEEE 1588 TOD Synchronizer Intel® FPGA IP Release Information
    • Ethernet Packet Classifier Intel® FPGA IP Release Information
2019.07.01 19.2
  • Renamed the Supported Devices sections to Release Information in the respective chapters to include IP release information as well as supported devices.
  • Added support for Intel® Stratix® 10 and Intel® Cyclone® 10 GX devices in the Time-of-day Clock and Time-of-day Synchronizer chapters.
  • Added support for Intel® Stratix® 10 devices in the Packet Classifier chapter.
2018.12.03 18.0
  • Rebranded as Intel.
  • Renamed the following Ethernet design example component names as per Intel rebranding:
    • "Ethernet IEEE 1588 TOD Synchronizer" to "Ethernet IEEE 1588 TOD Synchronizer Intel FPGA IP"
    • "Ethernet IEEE 1588 Time of Day Clock" to "Ethernet IEEE 1588 Time of Day Clock Intel FPGA IP"
    • "Ethernet Packet Classifier" to "Ethernet Packet Classifier Intel FPGA IP"
  • Updated the following topics:
    • Time-of-day Clock
    • Using the TOD Clock
  • Updated Table: Register Description to correct the byte offsets of SecondsL, NanoSec, Reserved, Period, AdjustPeriod, AdjustCount, DriftAdjust, DriftAdjustRate, OffsetNS, OffsetFNS, JitterTimer, JitterAdjust, WanderTimerLSB, and WanderAdjust registers.
  • Made editorial updates throughout the document.
Date Version Changes
March 2017 2017.03.08
  • Added a new topic: Correcting ToD Offset.
  • Updated the "Time-of-day Signals Description" table.
  • Added resource utilization for Arria 10 Devices for 16.1 release:
    • "Time-of-day Clock" section
    • "Time-of-day Synchronizer" section
    • "Packet Classifier" section
May 2016 2016.05.02 Initial release.
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