Ethernet Design Example Components User Guide

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ID 683044
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. Time-of-day Clock 2. Time-of-day Synchronizer 3. Packet Classifier 4. Ethernet Design Example Components User Guide Archives 5. Document Revision History for the Ethernet Design Example Components User Guide
1. Time-of-day Clock x
1.1. Release Information 1.2. Resource Utilization 1.3. Configuring the TOD Clock 1.4. Using the TOD Clock 1.5. Interface Signals 1.6. Configuration Registers
1.1. Release Information x
1.1.1. Pulse Per Second Device Speed Grade Support
1.4. Using the TOD Clock x
1.4.1. Adjusting TOD Drift 1.4.2. Adjusting Offset, Jitter, and Wander 1.4.3. Correcting TOD Offset 1.4.4. IOPLL and TOD Setup for Pulse Per Second (Advanced Accuracy Mode)
1.4.4. IOPLL and TOD Setup for Pulse Per Second (Advanced Accuracy Mode) x
1.4.4.1. IOPLL and TOD Setup using Dynamic Phase Shift Interface 1.4.4.2. IOPLL and TOD Setup using IOPLL Reconfig IP
1.5. Interface Signals x
1.5.1. Avalon Memory-Mapped Signals 1.5.2. Time-of-day Signals 1.5.3. Pulse-Per-Second Signals 1.5.4. Clocking Requirements
2. Time-of-day Synchronizer x
2.1. Release Information 2.2. Resource Utilization 2.3. Configuring the TOD Synchronizer 2.4. Using the TOD Synchronizer 2.5. Interface Signals
2.4. Using the TOD Synchronizer x
2.4.1. Sampling Clock Frequency
3. Packet Classifier x
3.1. Release Information 3.2. Resource Utilization 3.3. Configuring the Packet Classifier 3.4. Interface Signals
3.4. Interface Signals x
3.4.1. Clock and Reset Signals 3.4.2. Avalon® Streaming Interface Signals 3.4.3. Control Signals
1. Time-of-day Clock
2. Time-of-day Synchronizer
3. Packet Classifier
4. Ethernet Design Example Components User Guide Archives
5. Document Revision History for the Ethernet Design Example Components User Guide

2.3. Configuring the TOD Synchronizer

In the Quartus® Prime software, instantiate the TOD Synchronizer by selecting Ethernet IEEE 1588 TOD Synchronizer Intel® FPGA IP from the IP Catalog or Platform Designer (Interface Protocols > Ethernet > Reference Design Components). Specify the following parameters.

Table 20.  TOD Synchronizer Parameters Description
Name Valid Values Description
TOD_MODE 0, 1 Specifies the format of the time of day.
  • 0: 64 bits. 48 bits nanosecond and 16 bits fractional nanosecond.
  • 1: 96 bits. 48 bits seconds, 32 bits nanosecond and 16 bits fractional nanosecond.
The default value is 1.
SYNC_MODE 0 – 18 Specifies the synchronization type between the master and target TOD clocks.
  • 0: 125-MHz master TOD clock and 156.25 MHz target TOD clock.
  • 1: 156.25-MHz master TOD clock and 125-MHz target TOD clock.
  • 2: The frequencies of the master and target TOD clocks are the same, between 125 MHz and 402.83 MHz. This synchronization type supports different phase or PPM. Ensure that you also specify the period of the master and target clocks using the PERIOD_NSEC and PERIOD_FNSEC parameters.
  • 3: 156.25-MHz master TOD clock and 312.5-MHz target TOD clock.
  • 4: 312.5-MHz master TOD clock and 156.25-MHz target TOD clock.
  • 5: 125-MHz master TOD clock and 312.5-MHz target TOD clock.
  • 6: 312.5-MHz master TOD clock and 125-MHz target TOD clock.
  • 7: 125-MHz master TOD clock and 390.625-MHz target TOD clock.
  • 8: 390.625-MHz master TOD clock and 125-MHz target TOD clock.
  • 9: 156.25-MHz master TOD clock and 390.625-MHz target TOD clock.
  • 10: 390.625-MHz master TOD clock and 156.25-MHz target TOD clock.
  • 11: 312.5-MHz master TOD clock and 390.625-MHz target TOD clock.
  • 12: 390.625-MHz master TOD clock and 312.5-MHz target TOD clock.
  • 13: 125-MHz master TOD clock and 62.5-MHz target TOD clock.
  • 14: 156.25-MHz master TOD clock and 62.5-MHz target TOD clock.
  • 15: 312.5-MHz master TOD clock and 62.5-MHz target TOD clock.
  • 16: Reserved.
  • 17: Reserved.
  • 18: 125-MHz master TOD clock and 402.83-MHz target TOD clock.

The default value is 1.
PERIOD_NSEC 0 – 4'hF Specifies the respective 4-bit nanosecond field for the reset value for the following clock frequencies:
  • 125 MHz: Set this parameter to 4'h8 for 8 ns.
  • 156.25 MHz: Set this parameter to 4'h6 for 6.4 ns. This value is the default value.
  • 312.5 MHz: Set this parameter to 4'h3 for 3.2 ns.
  • 390.625 MHz: Set this parameter to 4'h2 for 2.56 ns.
  • 402.83 MHz: Set this parameter to 4’h2 for 2.482 ns.

This parameter is only applicable for SYNC_MODE = 2.

PERIOD_FNSEC 0 – 16h'FFFF Specifies the respective 16-bit fractional nanosecond field for the reset value for the following clock frequencies:
  • 125 MHz: Set this parameter to 16'h0 for 8 ns.
  • 156.25 MHz: Set this parameter to 16'h6666 for 6.4 ns. This value is the default value.
  • 312.5 MHz: Set this parameter to 16'h3333 for 3.2 ns.
  • 390.625 MHz: Set this parameter to 16'h8F5C for 2.56 ns.
  • 402.83 MHz: Set this parameter to 16’h7B80 for 2.482 ns.

This parameter is only applicable for SYNC_MODE = 2.

SAMPLE_SIZE 64, 128, or 256 Specifies the number of samples to use in calculating the FIFO buffer’s fill level. More samples results in a more accurate estimation of the fill level. However, the calculation time increases with the number of samples.

The default value is 64.

This parameter is not applicable for SYNC_MODE = 18.

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