Ethernet Design Example Components User Guide

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ID 683044
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. Time-of-day Clock 2. Time-of-day Synchronizer 3. Packet Classifier 4. Ethernet Design Example Components User Guide Archives 5. Document Revision History for the Ethernet Design Example Components User Guide
1. Time-of-day Clock x
1.1. Release Information 1.2. Resource Utilization 1.3. Configuring the TOD Clock 1.4. Using the TOD Clock 1.5. Interface Signals 1.6. Configuration Registers
1.1. Release Information x
1.1.1. Pulse Per Second Device Speed Grade Support
1.4. Using the TOD Clock x
1.4.1. Adjusting TOD Drift 1.4.2. Adjusting Offset, Jitter, and Wander 1.4.3. Correcting TOD Offset 1.4.4. IOPLL and TOD Setup for Pulse Per Second (Advanced Accuracy Mode)
1.4.4. IOPLL and TOD Setup for Pulse Per Second (Advanced Accuracy Mode) x
1.4.4.1. IOPLL and TOD Setup using Dynamic Phase Shift Interface 1.4.4.2. IOPLL and TOD Setup using IOPLL Reconfig IP
1.5. Interface Signals x
1.5.1. Avalon Memory-Mapped Signals 1.5.2. Time-of-day Signals 1.5.3. Pulse-Per-Second Signals 1.5.4. Clocking Requirements
2. Time-of-day Synchronizer x
2.1. Release Information 2.2. Resource Utilization 2.3. Configuring the TOD Synchronizer 2.4. Using the TOD Synchronizer 2.5. Interface Signals
2.4. Using the TOD Synchronizer x
2.4.1. Sampling Clock Frequency
3. Packet Classifier x
3.1. Release Information 3.2. Resource Utilization 3.3. Configuring the Packet Classifier 3.4. Interface Signals
3.4. Interface Signals x
3.4.1. Clock and Reset Signals 3.4.2. Avalon® Streaming Interface Signals 3.4.3. Control Signals
1. Time-of-day Clock
2. Time-of-day Synchronizer
3. Packet Classifier
4. Ethernet Design Example Components User Guide Archives
5. Document Revision History for the Ethernet Design Example Components User Guide

1.3. Configuring the TOD Clock

In the Quartus® Prime software, instantiate the TOD clock by selecting Ethernet IEEE 1588 Time of Day Clock Intel® FPGA IP from the IP Catalog or Platform Designer (Interface Protocols > Ethernet > Reference Design Components). Specify the following parameters.

Table 8.  TOD Clock Parameters Description
Name Value Default Value Description
Enable high clock frequency mode (PERIOD_CLOCK_FREQUENCY) On or Off On

Turn off this parameter if the MAC connected to the TOD clock requires low period clock frequency, such as the Triple-speed Ethernet or legacy 10G Ethernet MAC. For this setting, the nanosecond field in the Period and AdjustPeriod registers is 9 bits wide.

Turn on this parameter if the MAC connected to the TOD clock requires high period clock frequency, such as Low-latency 10G Ethernet, 25G Ethernet, or 40G/100G Ethernet MAC. For this setting, the nanosecond field in the Period and AdjustPeriod registers is 4 bits wide.

Enable offset, jitter, and wander supports (OFFSET_JITTER_WANDER_EN) On or Off Off Turn on this parameter to enable the offset, jitter, and wander timers. This parameter is available only when high clock frequency mode is disabled (PERIOD_CLOCK_FREQUENCY= 0).
DEFAULT_NSEC_PERIOD 0 – n 0x0006 The reset value of the nanosecond field in the Period register.

n is 0xF if the nanosecond field is 4 bits wide. Otherwise, n is 0x1FF.

DEFAULT_FNSEC_PERIOD 0 – 0xFFFF 0x6666 The reset value of the fractional nanosecond field in the Period register.
DEFAULT_NSEC_ADJPERIOD 0 – n 0x0006 The reset value of the nanosecond field in the AdjustPeriod register.

n is 0xF if the nanosecond field is 4 bits wide. Otherwise, n is 0x1FF.

DEFAULT_FNSEC_ADJPERIOD 0 – 0xFFFF 0x6666 The reset value of the fractional nanosecond field in the AdjustPeriod register.
Table 9.  Pulse Per Second Parameter DescriptionPulse per second parameters are only supported in Stratix® 10 and Agilex™ 7 devices with specific core speed grades. For more information, refer to Pulse Per Second Device Speed Grade Support.
Name Value Default Value Description
Enable pulse per second interface On or Off Off Turn on this parameter to enable pulse per second (PPS) feature of TOD.

IP needs to be regenerated if you modify this parameter.

Accuracy mode Basic or Advanced Basic

Basic: Generates pps pulse with <TOD period> accuracy.

Advanced: Generates pps pulse with 2 ns accuracy.

Advanced accuracy mode requires additional IOPLL instantiation with specific clock settings and with Enable access to dynamic phase shift ports selected. See Section IOPLL and TOD Setup for Pulse Per Second (Advanced Accuracy Mode) for the guidelines.

IP needs to be regenerated if you modify this parameter.

Pulse width 2 - 125,000 2

Defines the number of clock cycles the pps pulse will stay asserted, based on period_clk.

For example, when Pulse width is set to 2, the PPS pulse width equals to 2 clock cycles of period_clk.

PLL scan clock frequency

 50 MHz - 100 MHz 100 MHz

This parameter is only available if Advanced Accuracy Mode is enabled.

The frequency of scan clock feeds to the corresponding IOPLL.

Time of Day PPS feature currently supports only scan clock frequency of 50 MHz to 100 MHz regardless of the IOPLL support range.

Round down the clock frequency and enter only the integer value. For example, enter 81 MHz for 81.25 MHz scan clock frequency.

PLL unit phase shift

 1/8 of IOPLL VCO clock period 100 ps

This parameter is only available if Advanced Accuracy Mode is enabled.

Minimum phase shift in picosecond is achievable by corresponding IOPLL in single phase shift cycle. The value equals to 1/8 of IOPLL VCO clock period. Round down the clock frequency by entering only the integer value.

For example:

VCO clock frequency = 1250 MHz

VCO clock period = 800 ps

PLL unit phase shift = 1/8 x 800 = 100ps
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