F-Tile 25G Ethernet Intel® FPGA IP Design Example User Guide

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ID 750200
Date 11/29/2023
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. F-Tile 25G Ethernet Single-Channel Design Example 3. F-Tile 25G Ethernet Single Channel Design Example with Dynamic Reconfiguration 4. F-Tile 25G Ethernet Intel FPGA IP Design Example User Guide Archives 5. Document Revision History for F-Tile 25G Ethernet Intel® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design Example 1.3. Generating Tile Files 1.4. Simulating the F-Tile 25G Ethernet Intel FPGA IP Design Example Testbench 1.5. Compiling and Configuring the Design Example in Hardware 1.6. Testing the F-Tile 25G Ethernet Intel FPGA IP Hardware Design Example
1.2. Generating the Design Example x
1.2.1. Design Example Parameters
2. F-Tile 25G Ethernet Single-Channel Design Example x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Compilation 2.6. Hardware Testing
2.3. Functional Description x
2.3.1. Design Components
2.4. Simulation x
2.4.1. Testbench 2.4.2. Simulation Design Example Components 2.4.3. Test Case
2.6. Hardware Testing x
2.6.1. Test Procedure
3. F-Tile 25G Ethernet Single Channel Design Example with Dynamic Reconfiguration x
3.1. Features 3.2. Hardware and Software Requirements 3.3. Functional Description 3.4. Simulation 3.5. Hardware Testing
3.3. Functional Description x
3.3.1. Design Components
3.4. Simulation x
3.4.1. Testbench 3.4.2. Simulation Design Example Components 3.4.3. Test Case—Single-Channel Design Example with Dynamic Reconfiguration
3.5. Hardware Testing x
3.5.1. Test Procedure
1. Quick Start Guide
2. F-Tile 25G Ethernet Single-Channel Design Example
3. F-Tile 25G Ethernet Single Channel Design Example with Dynamic Reconfiguration
4. F-Tile 25G Ethernet Intel FPGA IP Design Example User Guide Archives
5. Document Revision History for F-Tile 25G Ethernet Intel® FPGA IP Design Example User Guide

3.4.3. Test Case—Single-Channel Design Example with Dynamic Reconfiguration

The simulation test case performs the following actions:

  1. Instantiates F-Tile 25G Ethernet Intel® FPGA IP, dynamic reconfiguration controller, and SYS PLL.
  2. Starts up the design example with an operation speed of 25G.
  3. Waits for RX clock and RX alignment to settle.
  4. Transmits and receives 10 valid 64-bit data on 25G speed.
  5. The testbench performs the dynamic reconfiguration operation to switch the speed to 10G.
  6. Waits for RX clock and RX alignment to settle.
  7. Transmits and receives 10 valid 64-bit data on 10G speed.
  8. The testbench performs the dynamic reconfiguration operation to switch the speed back to 25G.
  9. Waits for RX clock and RX alignment to settle.
  10. Transmits and receives 10 valid 64-bit data on 25G speed.
  11. The successful testbench displays "Testbench complete.".
The following sample output illustrates a successful simulation test run:
Level Two Title