F-Tile 25G Ethernet Intel® FPGA IP Design Example User Guide

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ID 750200
Date 11/29/2023
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. F-Tile 25G Ethernet Single-Channel Design Example 3. F-Tile 25G Ethernet Single Channel Design Example with Dynamic Reconfiguration 4. F-Tile 25G Ethernet Intel FPGA IP Design Example User Guide Archives 5. Document Revision History for F-Tile 25G Ethernet Intel® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design Example 1.3. Generating Tile Files 1.4. Simulating the F-Tile 25G Ethernet Intel FPGA IP Design Example Testbench 1.5. Compiling and Configuring the Design Example in Hardware 1.6. Testing the F-Tile 25G Ethernet Intel FPGA IP Hardware Design Example
1.2. Generating the Design Example x
1.2.1. Design Example Parameters
2. F-Tile 25G Ethernet Single-Channel Design Example x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Compilation 2.6. Hardware Testing
2.3. Functional Description x
2.3.1. Design Components
2.4. Simulation x
2.4.1. Testbench 2.4.2. Simulation Design Example Components 2.4.3. Test Case
2.6. Hardware Testing x
2.6.1. Test Procedure
3. F-Tile 25G Ethernet Single Channel Design Example with Dynamic Reconfiguration x
3.1. Features 3.2. Hardware and Software Requirements 3.3. Functional Description 3.4. Simulation 3.5. Hardware Testing
3.3. Functional Description x
3.3.1. Design Components
3.4. Simulation x
3.4.1. Testbench 3.4.2. Simulation Design Example Components 3.4.3. Test Case—Single-Channel Design Example with Dynamic Reconfiguration
3.5. Hardware Testing x
3.5.1. Test Procedure
1. Quick Start Guide
2. F-Tile 25G Ethernet Single-Channel Design Example
3. F-Tile 25G Ethernet Single Channel Design Example with Dynamic Reconfiguration
4. F-Tile 25G Ethernet Intel FPGA IP Design Example User Guide Archives
5. Document Revision History for F-Tile 25G Ethernet Intel® FPGA IP Design Example User Guide

3.3.1. Design Components

Table 8.  Design Components
Component Description
F-Tile 25G Ethernet Intel FPGA IP

Consists of MAC, PCS, and Transceiver PHY, with the following configuration:

  • Core Variant: MAC+PCS+PMA
  • Enable flow control: Optional
  • Enable link fault generation: Optional
  • Enable preamble passthrough: Optional
  • Enable statistics collection: Optional
  • Enable MAC statistics counters: Optional
  • Enable Native PHY Debug Master Endpoint (NPDME): Optional
  • Reference clock frequency: 156.25
SYS PLL Generates reference and system clocks for the 10G/25G transceivers.
Client logic Consists of:
  • Traffic generator, which generates burst packets to the F-Tile 25G Ethernet Intel FPGA IP core for transmission.
  • Traffic monitor, which monitors burst packets that are coming from the F-Tile 25G Ethernet Intel FPGA IP core.
Source and Probe Source and probe signals, including system reset input signal, which you can use for debugging.
Dynamic reconfiguration controller Dynamic reconfiguration controller is generated when you generate the single-channel design example with dynamic reconfiguration.
Level Two Title