E-Tile Hard IP Agilex™ 7 Design Example User Guide: Ethernet, E-tile CPRI PHY and Dynamic Reconfiguration

ID 683860
Date 4/30/2024
Public
Document Table of Contents

2.1.6. Testing the E-tile Ethernet IP for Intel Agilex® 7 FPGA Hardware Design Example

After you compile the E-tile Ethernet IP for Intel Agilex® 7 FPGA core design example and configure it on your Agilex™ 7 device, you can use the System Console to program the IP core and its embedded Native PHY IP core registers.