E-Tile Hard IP Agilex™ 7 Design Example User Guide: Ethernet, E-tile CPRI PHY and Dynamic Reconfiguration

ID 683860
Date 4/30/2024
Public
Document Table of Contents

2.5. Document Revision History for the E-tile Hard IP for Ethernet Agilex™ 7 FPGA IP Design Example User Guide

Document Version Quartus® Prime Version IP Version Changes
2023.05.26 23.1 24.0.1
  • Updated the Fast Sim Model is supported in variants without PTP in Fast Sim Model in E-tile Ethernet IP for Intel Stratix 10 FPGA.
  • Updated Programming Intel FPGA Devices link in Compiling and Configuring the Design Example in Hardware.
  • Updated step 5 command to start_pma_init_adaptation_ex(1)/start_pma_02_init_adaptation_ex(2) in 100GE MAC+PCS with Optional (528,514) RS-FEC or (544,514) RS-FEC and Adaptation Flow Hardware Design Example under Testing the E-tile Ethernet IP for Intel Agilex 7 FPGA Hardware Design Example chapter.
  • Added steps to run simulation with the IEEE Ethernet standard specified interval in the following chapters:
    • 100GE MAC+PCS with Optional RS-FEC Dynamic Reconfiguration Simulation Design Example
    • Non-PTP E-tile Ethernet IP for Intel Agilex® 7 FPGA 100GE MAC+PCS with Optional RS-FEC Simulation Design Example
    • E-tile Ethernet IP for Intel Agilex® 7 FPGA 100GE MAC+PCS with Optional RS-FEC and PTP Simulation Design Example
    • Non-PTP 10GE/25GE MAC+PCS with Optional RS-FEC Simulation Design Example
2023.01.20 22.4 23.0.0
  • Added a new topic: Fast Sim Model for E-tile Ethernet IP for Intel Agilex 7 FPGA.
  • Fixed the broken links in Compiling and Configuring the Design Example in Hardware.
  • Updated the product family to "Intel Agilex 7".
2022.09.26 22.3 22.0.0 Made the following updates:
  • Corrected the link to the Agilex™ 7 F-Series Transceiver-SoC Development Kit web page
  • Added the Ethernet Adaptation Flow for 100G (CAUI-2) PAM4 <---> 100G (CAUI-4) NRZ Dynamic Reconfiguration Design Example section
  • Added the Additional Reconfig Options in Quartus® Prime Pro Edition software v22.2 for Agilex™ 7 E-tile section
2021.12.11 21.3 20.2.0
  • Added support for Questa simulator.
  • Removed support for NCSim simulator.
2021.08.04 21.2 20.2.0
  • Updated steps in the following section:
    • Generating the Design
    • Compiling and Configuring the Design Example in Hardware
  • Added new command setting: EnhancedPTPAccuracy.
  • Updated the design example support in Table: Supported Design Example Variants for 10GE/25GE.
  • Added a new signal for SyncE feature in Figure: 10GE/25GE MAC+PCS with Optional RS-FEC and PTP Hardware Design Example High Level Block Diagram and Table: 10GE/25GE Hardware Design Example Interface Signals.
2021.01.27 20.3 20.1.1 Added new topic: Ethernet Toolkit
2020.06.29 20.2 20.1.0 Revised Y1 description in the Compiling and Configuring the Design Example in Hardware section.
2019.12.30 19.4 19.4.0
  • Updated Table: List of Supported Design Example Variants to include hardware design example support.
  • Added hardware design example support for 10GE/25GE with optional RS-FEC design example.
  • Added hardware design example support for 100GE with optional RS-FEC design example.
  • Updated description of PMA adaptation setting in the Generating the Design section.
  • Added Asynchronous clock support for the 100GE MAC+PCS with (528,514) RS-FEC and PTP variant.
  • Restructured topics to improve the content flow.
2019.10.18 19.3 19.3.0 Initial Release.