E-Tile Hard IP Agilex™ 7 Design Example User Guide: Ethernet, E-tile CPRI PHY and Dynamic Reconfiguration

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ID 683860
Date 4/30/2024
Public
Document Table of Contents
Document Table of Contents x
1. About E-tile Hard IP Agilex™ 7 Design Example User Guide 2. E-Tile Ethernet IP for Agilex™ 7 FPGA Design Example 3. E-tile CPRI PHY Intel® FPGA IP Design Example 4. E-Tile Dynamic Reconfiguration Design Example 5. E-tile Hard IP Agilex™ 7 Design Examples User Guide Archives
2. E-Tile Ethernet IP for Agilex™ 7 FPGA Design Example x
2.1. Quick Start Guide 2.2. 10GE/25GE with Optional RS-FEC Design Examples 2.3. 100GE with Optional RS-FEC Design Example 2.4. Ethernet Toolkit Overview 2.5. Document Revision History for the E-tile Hard IP for Ethernet Agilex™ 7 FPGA IP Design Example User Guide
2.1. Quick Start Guide x
2.1.1. Directory Structure 2.1.2. Generating the Design 2.1.3. Simulating the E-tile Ethernet IP for Intel Agilex® 7 FPGA Design Example Testbench 2.1.4. Compiling the Compilation-Only Project 2.1.5. Compiling and Configuring the Design Example in Hardware 2.1.6. Testing the E-tile Ethernet IP for Intel Agilex® 7 FPGA Hardware Design Example
2.1.3. Simulating the E-tile Ethernet IP for Intel Agilex® 7 FPGA Design Example Testbench x
2.1.3.1. Fast Sim Model for E-tile Ethernet IP for Intel Agilex® 7 FPGA
2.1.6. Testing the E-tile Ethernet IP for Intel Agilex® 7 FPGA Hardware Design Example x
2.1.6.1. 10GE/25GE Design Example 2.1.6.2. 100GE MAC+PCS with Optional (528,514) RS-FEC or (544,514) RS-FEC and Adaptation Flow Hardware Design Example 2.1.6.3. 100GE PCS Only with Optional (528,514) RS-FEC or (544,514) RS-FEC, and Optional PTP Hardware Design Example
2.2. 10GE/25GE with Optional RS-FEC Design Examples x
2.2.1. Simulation Design Examples 2.2.2. Hardware Design Examples 2.2.3. 10GE/25GE Design Example Interface Signals 2.2.4. 10GE/25GE Design Examples Registers
2.2.1. Simulation Design Examples x
2.2.1.1. Non-PTP 10GE/25GE MAC+PCS with Optional RS-FEC Simulation Design Example 2.2.1.2. PTP 10GE/25GE MAC+PCS with Optional RS-FEC Simulation Design Example 2.2.1.3. 10GE/25GE PCS Only, OTN, or FlexE with Optional RS-FEC Simulation Design Example 2.2.1.4. 10GE/25GE Custom PCS with Optional RS-FEC Simulation Design Example
2.2.2. Hardware Design Examples x
2.2.2.1. 10GE/25GE MAC+PCS with Optional RS-FEC and PTP Hardware Design Example Components 2.2.2.2. 10GE/25GE PCS Only with Optional RS-FEC Hardware Design Example Components 2.2.2.3. 10GE/25GE Custom PCS with Optional RS-FEC Hardware Design Example
2.3. 100GE with Optional RS-FEC Design Example x
2.3.1. Simulation Design Examples 2.3.2. Hardware Design Examples 2.3.3. 100GE MAC+PCS with Optional RS-FEC Design Example Interface Signals 2.3.4. 100GE PCS with Optional RS-FEC Design Example Interface Signals 2.3.5. 100GE MAC+PCS with Optional RS-FEC Design Example Registers 2.3.6. 100GE PCS with Optional RS-FEC Design Example Registers
2.3.1. Simulation Design Examples x
2.3.1.1. Non-PTP E-tile Ethernet IP for Intel Agilex® 7 FPGA 100GE MAC+PCS with Optional RS-FEC Simulation Design Example 2.3.1.2. E-tile Ethernet IP for Intel Agilex® 7 FPGA 100GE MAC+PCS with Optional RS-FEC and PTP Simulation Design Example 2.3.1.3. E-tile Ethernet IP for Intel Agilex® 7 FPGA 100GE PCS Only with Optional RS-FEC Simulation Design Example 2.3.1.4. E-tile Ethernet IP for Intel Agilex® 7 FPGA 100GE OTN with Optional RS-FEC Simulation Design Example 2.3.1.5. E-tile Ethernet IP for Intel Agilex® 7 FPGA 100GE FlexE with Optional RS-FEC Simulation Design Example
2.3.2. Hardware Design Examples x
2.3.2.1. 100GE MAC+PCS with Optional RS-FEC and PMA Adaptation Flow Hardware Design Example Components 2.3.2.2. 100GE MAC+PCS with Optional RS-FEC and PTP Hardware Design Example 2.3.2.3. 100GE PCS with Optional RS-FEC Hardware Design Example Components 2.3.2.4. Ethernet Adaptation Flow for 100G (CAUI-2) PAM4 <---> 100G (CAUI-4) NRZ Dynamic Reconfiguration Design Example
2.4. Ethernet Toolkit Overview x
2.4.1. Features
3. E-tile CPRI PHY Intel® FPGA IP Design Example x
3.1. E-tile CPRI PHY Intel® FPGA IP Quick Start Guide 3.2. E-tile CPRI PHY Design Example Description 3.3. Document Revision History for the E-tile CPRI PHY Intel® FPGA IP Design Example User Guide
3.1. E-tile CPRI PHY Intel® FPGA IP Quick Start Guide x
3.1.1. Hardware and Software Requirements 3.1.2. Generating the Design 3.1.3. Directory Structure 3.1.4. Simulating the Design Example Testbench 3.1.5. Compiling the Compilation-Only Project 3.1.6. Compiling and Configuring the Design Example in Hardware 3.1.7. Testing the E-tile CPRI PHY Intel® FPGA IP Hardware Design Example
3.2. E-tile CPRI PHY Design Example Description x
3.2.1. Features 3.2.2. Simulation Design Example 3.2.3. Hardware Design Example 3.2.4. Interface Signals 3.2.5. Design Example Register Map for Reconfiguration
4. E-Tile Dynamic Reconfiguration Design Example x
4.1. Quick Start Guide 4.2. 10G/25G Ethernet Dynamic Reconfiguration Design Examples 4.3. 25G Ethernet to CPRI Dynamic Reconfiguration Design Example 4.4. CPRI Dynamic Reconfiguration Design Examples 4.5. 100G Ethernet Dynamic Reconfiguration Design Example 4.6. Document Revision History for the E-Tile Dynamic Reconfiguration Design Example
4.1. Quick Start Guide x
4.1.1. Directory Structure 4.1.2. Generating the Design 4.1.3. Simulating the E-Tile Dynamic Reconfiguration Design Example Testbench 4.1.4. Compiling and Configuring the Design Example in Hardware 4.1.5. Testing the E-Tile Dynamic Reconfiguration Hardware Design Example
4.1.2. Generating the Design x
4.1.2.1. Design Example Parameters
4.1.3. Simulating the E-Tile Dynamic Reconfiguration Design Example Testbench x
4.1.3.1. Running the Simulation 4.1.3.2. Generating New HEX File Using Eclipse-based Ashling RiscFree IDE Tool 4.1.3.3. Performing the Link Initialization
4.1.5. Testing the E-Tile Dynamic Reconfiguration Hardware Design Example x
4.1.5.1. Running the Design Example in Hardware 4.1.5.2. Power Management Setting for Agilex™ 7 Transceiver Signal Integrity Development Kit
4.2. 10G/25G Ethernet Dynamic Reconfiguration Design Examples x
4.2.1. Functional Description 4.2.2. Simulation Design Examples 4.2.3. Hardware Design Examples 4.2.4. 10GE/25GE Design Example Interface Signals 4.2.5. 10GE/25GE Design Examples Registers 4.2.6. Dynamic Reconfiguration Flow for 25GbE PTP FEC to 25GbE PTP Non-FEC
4.2.1. Functional Description x
4.2.1.1. Clocking Scheme
4.2.2. Simulation Design Examples x
4.2.2.1. 10GE/25GE MAC+PCS with RS-FEC and PTP Simulation Dynamic Reconfiguration Design Example Components 4.2.2.2. 10GE/25GE MAC+PCS with RS-FEC Simulation Dynamic Reconfiguration Design Example Components
4.2.3. Hardware Design Examples x
4.2.3.1. 10GE/25GE MAC+PCS with RS-FEC and PTP Hardware Dynamic Reconfiguration Design Example Components 4.2.3.2. 10GE/25GE MAC+PCS with RS-FEC Hardware Dynamic Reconfiguration Design Example Components
4.3. 25G Ethernet to CPRI Dynamic Reconfiguration Design Example x
4.3.1. Functional Description 4.3.2. Simulation Design Examples 4.3.3. Hardware Design Examples 4.3.4. 25G Ethernet to CPRI Design Example Interface Signals 4.3.5. 25G Ethernet to CPRI Design Examples Registers 4.3.6. Dynamic Reconfiguration Flow for 25GbE PTP FEC to 24G CPRI FEC
4.3.1. Functional Description x
4.3.1.1. Clocking Scheme 4.3.1.2. Reset
4.3.2. Simulation Design Examples x
4.3.2.1. 25GE MAC+PCS with RS-FEC and PTP to CPRI Simulation Dynamic Reconfiguration Design Example Components
4.3.3. Hardware Design Examples x
4.3.3.1. 25GE MAC+PCS with RS-FEC and PTP to CPRI Hardware Dynamic Reconfiguration Design Example Components
4.4. CPRI Dynamic Reconfiguration Design Examples x
4.4.1. Functional Description 4.4.2. Simulation Design Examples 4.4.3. Hardware Design Examples 4.4.4. CPRI Design Example Interface Signals 4.4.5. CPRI Design Example Registers 4.4.6. Dynamic Reconfiguration Flow for 24G CPRI FEC to 24G CPRI Non-FEC
4.4.1. Functional Description x
4.4.1.1. Clocking Scheme
4.4.2. Simulation Design Examples x
4.4.2.1. 24G CPRI PHY with RS-FEC Simulation Dynamic Reconfiguration Design Example Components 4.4.2.2. 9.8G CPRI PHY Simulation Dynamic Reconfiguration Design Example Components
4.4.3. Hardware Design Examples x
4.4.3.1. CPRI PHY with RS-FEC Hardware Dynamic Reconfiguration Design Example Components
4.5. 100G Ethernet Dynamic Reconfiguration Design Example x
4.5.1. Functional Description 4.5.2. Testing the 100G Ethernet Dynamic Reconfiguration Hardware Design Example 4.5.3. Simulation Design Examples 4.5.4. 100GE DR Hardware Design Examples 4.5.5. 100G Ethernet Dynamic Reconfiguration Design Example Interface Signals 4.5.6. 100G Ethernet Dynamic Reconfiguration Examples Registers 4.5.7. Steps to Enable FEC 4.5.8. Steps to Disable FEC
4.5.2. Testing the 100G Ethernet Dynamic Reconfiguration Hardware Design Example x
4.5.2.1. Dynamic Reconfiguration Flow in 100G Ethernet Dynamic Reconfiguration Example Design
4.5.3. Simulation Design Examples x
4.5.3.1. 100GE MAC+PCS with Optional RS-FEC Dynamic Reconfiguration Simulation Design Example 4.5.3.2. Simulating the E-tile Ethernet IP for Intel Agilex® 7 FPGA Design Example Testbench
4.5.4. 100GE DR Hardware Design Examples x
4.5.4.1. 100GE MAC+PCS with Optional RS-FEC Dynamic Reconfiguration Hardware Design Example Components
4.5.7. Steps to Enable FEC x
4.5.7.1. Configuring for 100G NRZ with RSFEC [KR-FEC (528,514)] 4.5.7.2. Configuring for 100G NRZ with RSFEC [KP-FEC (544,514)] 4.5.7.3. Configuring for 100G PAM4 with RSFEC [KP-FEC (544,514)]
1. About E-tile Hard IP Agilex™ 7 Design Example User Guide
2. E-Tile Ethernet IP for Agilex™ 7 FPGA Design Example
3. E-tile CPRI PHY Intel® FPGA IP Design Example
4. E-Tile Dynamic Reconfiguration Design Example
5. E-tile Hard IP Agilex™ 7 Design Examples User Guide Archives

2.1.5. Compiling and Configuring the Design Example in Hardware

To compile the hardware design example and configure it on your Agilex™ 7 device, follow these steps:

  1. Ensure hardware design example generation is complete.
  2. In the Quartus® Prime Pro Edition software, open the Quartus® Prime project <design_example_dir>/hardware_test_design/alt_ehip3.qpf.
  3. On the Processing menu, click Start Compilation.
  4. After successful compilation, a .sof file is available in <design_example_dir>/hardware_test_design/output_files directory. Follow these steps to program the hardware design example on the Agilex™ 7 device:
    1. Connect Intel Agilex® 7 F-Series Transceiver-SoC Development Kit to the host computer.
    2. Launch the Clock Control application, which is part of the development kit, and set new frequencies for the design example. Below is the frequency setting in the Clock Control application:
      • U37 (Si5338), CLK1—100MHz
      • For SyncE-enabled design example:
        • LMK05028, IN0—Set to the frequency of o_clk_rec_div66 signal.
          • For 10G variant, set to 156.25MHz.
          • For 25G variant, set to 390.625MHz.
        • LMK05028, OUT2—Set to the PHY Reference Frequency specified in the PMA Options 10GE/25GE settings under 10GE/25GE tab.
      • For non SyncE-enabled design example:
        • Y2 (Si549) - Set to the PHY Reference Frequency of the design.
          • For 10GE/25GE variant, select 10GE/25GE tab and locate the PMA Options 10GE/25GE setting.
          • For 100GE variant, select 100GE tab and locate the PMA Options 100GE setting.
        Note: For steps to configure Clock Controller application, refer to the Control on-board clock through Clock Controller GUI section of Agilex™ 7 F-Series Transceiver-SoC Development Kit User Guide.
    3. On the Tools menu, click Programmer.
    4. In the Programmer, click Hardware Setup.
    5. Select a programming device.
    6. Select and add the Intel Agilex® 7 F-Series Transceiver-SoC Development Kit to which your Quartus® Prime Pro Edition session can connect.
    7. Ensure that Mode is set to JTAG.
    8. Select the Agilex™ 7 device and click Add Device. The Programmer displays a block diagram of the connections between the devices on your board.
    9. In the row with your .sof, check the box for the .sof.
    10. Check the box in the Program/Configure column.
    11. Click Start.
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