Intel® Quartus® Prime Standard Edition User Guide: Platform Designer

ID 683364
Date 12/15/2018
Public
Document Table of Contents

5.17.1. Static Components

Static components always generate the same output, regardless of their parameterization. Components that instantiate static components must have only static children.

A design file that is static between all parameterizations of a component can only instantiate other static design files. Since static IPs always render the same HDL regardless of parameterization, Platform Designer generates static IPs only once across multiple instantiations, meaning they have the same top-level name set.

Typical Usage of the add_hdl_instance Command for Static Components

package require -exact qsys 14.0 
  	
set_module_property name add_hdl_instance_example  	
add_fileset synth_fileset QUARTUS_SYNTH synth_callback	
set_fileset_property synth_fileset TOP_LEVEL basic_static
set_module_property elaboration_callback elab	

proc elab {} {	
  # Actual API to instantiate an IP Core	
  add_hdl_instance emif_instance_name altera_mem_if_ddr3_emif	

  # Make sure the parameters are set appropriately	
  set_instance_parameter_value emif_instance_name SPEED_GRADE {7}
  ...
  }	
proc synth_callback { output_name } {	
  add_fileset_file "basic_static.v" VERILOG PATH basic_static.v	
}

Top-Level HDL Instance and Wrapper File Created by Platform Designer

In this example, Platform Designer generates a wrapper file for the instance name specified in the _hw.tcl file.

//Top Level Component HDL
module basic_static (input_wire, output_wire, inout_wire);
input [31:0] input_wire;
output [31:0] output_wire;
inout [31:0] inout_wire;

// Instantiation of the instance added via add_hdl_instance 
// command. This is an example of how the instance added via 
// the add_hdl_instance command can be used 
// in the top-level file of the component.

emif_instance_name fixed_name_instantiation_in_top_level(
.pll_ref_clk (input_wire), // pll_ref_clk.clk
.global_reset_n (input_wire), // global_reset.reset_n
.soft_reset_n (input_wire), // soft_reset.reset_n
...
... );
endmodule

//Wrapper for added HDL instance
// emif_instance_name.v
// Generated using ACDS version 14.0 

`timescale 1 ps / 1 ps
module emif_instance_name (
input wire pll_ref_clk, // pll_ref_clk.clk
input wire global_reset_n, // global_reset.reset_n
input wire soft_reset_n, // soft_reset.reset_n
output wire afi_clk, // afi_clk.clk
...
...);
example_addhdlinstance_system
_add_hdl_instance_example_0_emif_instance
_name_emif_instance_name emif_instance_name (

.pll_ref_clk (pll_ref_clk), // pll_ref_clk.clk
.global_reset_n (global_reset_n), // global_reset.reset_n
.soft_reset_n (soft_reset_n), // soft_reset.reset_n
...	
...);
endmodule